The Neuromorphic Analog Signal Processing technology platform plays a principal role in the development and production of neuromorphic front-end chips. It enables conversion of trained digital neural networks into an accurate math model for subsequent manufacturing of analog neuromorphic cores.  The use of specially designed EDA flow is crucial in creation of the very first silicon – per application – and ensuring a quick time to market for the chip.

POLYN’s “miracle ingredient” is a proprietary NASP T-compiler that transforms the neural network simulation into a netlist suitable for silicon integration.

To ensure the robust silicon design, it is necessary to use the advanced, proven tools offered by the EDA industry. In close cooperation with our EDA vendor, POLYN developed new approaches for using standard tools and a new design flow specific to analog processing tasks.  The resulting flow enables seamless transition from the Verilog netlist to the GDSII. The flow can be implemented at any silicon foundry supporting custom layering for high-ohmic resistors. These resistors represent the weights of the neural network and are fabricated between top metal layers to save CMOS area and minimize the product costs.

Since every weight in the neural network could have a unique value, especially if high-precision weights are used, we developed a custom flow to generate layouts for all these resistors in what is a complicated design task.  These layouts are unified and allow building a resistor array with good area utilization and sufficient matching.

To enable resistor weights placement on top of the analog CMOS circuitry, we developed a “Cover-Cell” Place-and-Route (P&R) flow. This P&R flow is a two-step version of a standard digital-on-top flow. At the first step the design cells are placed using an optimization criterion of wire-length, without timing and logic optimization. The main concern for placement is the CMOS circuitry proximity to its weight cells (resistors) achieved by using attraction/magnet type placement as the optimization method. This minimizes routing congestions, provides better connectivity, and, crucially, minimizes parasitics that could affect the analog circuit performance. We set the CMOS circuitry attribute as “COVER” and the resistor cells attribute as “CORE” and use a standard EDA P&R algorithm to perform placement efficiently.

So we first make the CMOS circuitry pre-alignment, then wire-length driven localization, followed by reference hierarchy and Route and DCR correction.

Using this approach, we managed to run implementation of about 4 million cells. This size neural network implementation is more than sufficient for signal pre-processing for most IIoT applications. It takes less than 24 hours to complete one run, leaving enough time for trial and adjustments without compromising a project schedule or creating unnecessary risks. This flexible and robust approach and the full-custom design flow are fundamental for quick and efficient realization of any client needs in a compact and energy-efficient NASP-based product.