Neuromorphic Analog Signal Processing (NASP)
Neuromorphic computing is a method of computer engineering where the system elements mimic the human brain and nervous system, in hardware and software. Neuromorphic systems provide both fast computation and low power consumption, handling many operations simultaneously. Among other things, it means they are fault-tolerant and capable to produce results after some elements have failed.
A neuromorphic chip imitates the brain through elements that implement “neurons”, nodes that process information, and “axons”, connections with weights between the nodes that transfer electrical signals using analog circuitry. An electric signal modulation mimics the brain signal variation.
According to the Decadal Plan for Semiconductors by Semiconductor Research Corporation, the first among major shifts that will define the future of semiconductors and ICT, will be the analog data deluge: Fundamental breakthroughs in analog hardware are required to generate smarter world-machine interfaces that can sense, perceive, and reason.
In our neuromorphic analog solution, neurons are physically implemented as an analog circuitry elements according to the mathematical simulation of a single neuron.
As new sensors are poised for deployment at the edge, data processing emerges as a significant challenge. This is where POLYN’s revolutionary technology, which places the signal neuromorphic analog processing directly next to the sensor, comes into play, efficiently handling a massive amount of raw data before sending it to the host.
This shift is especially important for Physical AI – systems that interact with the real world continuously. Unlike cloud AI, physical systems cannot tolerate communication delays or unpredictable power budgets.
NO FEAR of DATA TSUNAMI
Use of Embeddings
Embeddings are representations that a trained autoencoder neural network forms in its deep hidden layers. Embeddings contain densely packed the most significant information about sensory input data.
Embeddings are used as input data for further processing, classification, and interpretation.
Use of embeddings for sensor data preprocessing reduces the noisy raw data flow by a factor of 1000, making it highly instrumental for various Edge AI applications.
SENSOR DATA FLOW REDUCED BY
NASP technology is ideal for real time Edge sensor signal processing (ESSP) appliances, providing small size, ultra-low power consumption and low latency.
NASP Convertor works with any standard Neural Net framework like Keras, Tensor Flow or others.
NASP receives any type of signal and processes raw sensor data using neuromorphic AI computations on sensor level without sending it to the cloud.
1Analog /digital signal input
2POLYN’s neuromorphic architecture processes input signals in a true parallel asynchronous mode providing unprecedented low latency and low power consumption. Calculations do not require CPU usage or memory access.
3NASP can use a pre-trained artificial neural network from any major ML framework (such as Tensor Flow, PyTorch, MXNet etc.) for the neuromorphic representation resulting in exceptional precision and accuracy.
NASP HYBRID SOLUTION
In NASP hybrid concept, the analog neuromorphic chip with fixed neural networks is responsible for pattern detection, based on embeddings and combined with a flexible algorithm, which could be any type, including an additional flexible neural network, responsible for the pattern interpretation and even retraining.
There is a well-known phenomenon of Machine Learning: after several hundred training cycles, also known as epochs, the deep convolutional neural network maintains fixed weights and structure of the first 80-90% of the layers, and in the following cycles, only the few last layers responsible for classification continue to change weights. This fact is used in transfer learning, which is a key to the hybrid NASP concept.
FROM a NEURAL NET TO the CHIP
The NASP platform synthesizes a true neuromorphic chip layout from any trained neural network
NASP Chip Production
Semiconductor fabs produce NASP chips with standard equipment and processes
Development Process
- Generate the final layout and GDSII format for a target Node and Fab