Technology

Neuromorphic Analog Signal Processing (NASP)

Ideal for New Generation of Front-end Devices in real time EDGE applications

Sensor level platform to synthesize a true neuromorphic Tiny AI chip layout from any trained neural network

Neural Net Design

Select a trained Neural Net or train the customer’s Neural Net

Math Model Simulation

Generated with NAPS Compiler:  D-MVP – Neural Network Software Simulation

NASP Chip Synthesis

The Math Model converted into the chip layout ready for production

NASP Chip Production

Semiconductor fabs produce NASP chips with standard equipment and processes

NASP Technology is ideal for real time EDGE sensor signal processing (ESSP) appliances, providing small size,  ultra-low power consumption and low lattency

NASP Convertor works with any standard Neural Net framework like Keras, TensorFlow or others

NASP receives any type of signals and processes raw sensor data using neuromorphic AI computations on sensor level without digitalizing analog signals 

1Direct analog /digital signal input  

2POLYN’s neuromorphic architecture processes input signals in a true parallel, asynchronous mode, which provides unprecedented low latency and low power consumption. Calculations do not require CPU usage or memory access.

3NASP can use a pre-trained artificial neural network from any major ML framework (such as TensorFlow, PyTorch, MXNet etc) for the neuromorphic representation resulting in exceptional precision and accuracy.

Development Process

PROTOTYPE NEURAL NET MODEL
NEURAL NET TRAINING AND CONVERSION
  • NN is provided by customer or Polyn assists the customer in NN selection
  • Fully functionable math model of NN
  • Data set collection and training process 
  • Accept of final functionality of trained NN
SYNTHESIS
NETLIST for the target CAD
  • Convert trained NN to Netlist for CAD and generate neurons library
  • Build CAD model of NASP block
  • Verification of NASP CAD model and NN model conformity 
IMPLEMENTATION
CHIP PRODUCTION
  • Generate final layout and GDSII format for target Node and Fab