SYNTHESIZABLE HARD IP BLOCK

POLYN CORE TECHNOLOGY DELIVERS A UNIQUE PRODUCT TO THE MARKET – A SYNTHESIZED NASP HARD IP BLOCK.
  • The Synthesized NASP Hard IP block is delivered as a NETLIST or GDSII layout format for integration with an IC or chiplet.
  • Direct analog (or digital) input (-s) and digital or analog output (-s).
  • Our neuromorphic architecture processes input signals in a true parallel, asynchronous mode, which provides unprecedented low latency and low power consumption. Calculations don’t require CPU usage or memory access.
  • We can use a pre-trained artificial neural network from any major ML framework (such as TensorFlow, PyTorch, MXNet etc) for our neuromorphic representation which will result in exceptional precision and accuracy.
NASP IP BLOCKS
for any type of Neural Net, from Polyn NN library or NN provided by Customer
HARD IP BLOCK FOR CHIPLET OR SEPARATE CHIP PRODUCTION
HARD IP BLOCK FOR IC INTEGRATION BY CUSTOMER PROJECT
DIGITAL PLATFORM TO SYNTHESIZE NASP FROM ANY NN BY CUSTOMER
*POLYN does not require an access to customer’s proprietary neural networks and data sets

NASP CHANGES THE AFE DEVICE PARADIGM

SENSORS
  • Mic
  • Temperature / Pressure
  • PPG and health monitoring
  • Chemicals sensors
  • Lidar/Radar / Ultrasound
  • Other analog sensors

DEPLOYMENT PROCESS

PROTOTYPE ON NEURAL NET MODEL
NEURAL NET DEPLOY BY CUSTOMER REQUEST
NN TRAINING AND CONVERSION
  • Find the best NN for customer needs.
  • NN is provided by Polyn specifically for customer needs or NN is provided by customer
  • Deploy fully functionable math model of NN
  • Data set collection and training process (by Polyn or by customer side)
  • Accept of final functionality of trained NN
  • Accept technology node and fab
SYNTHESES
NETLIST FOR THE TARGET CAD
NON MERGE CAD MODEL
  • Convert trained NN to Netlist for CAD and generate neurons library
  • Build CAD model of NASP block
  • CAD simulations and check math equal of Model NN and CAD NASP model
IMPLEMENTATION
GDSII FOR HARD BLOCK
OR CHIPLET PRODUCTION
  • Generate final layout and GDSII format for target Node and Fab.
  • Use as hard Block or for chiplet production