At a glance
- Moving raw sensor data off-chip costs more energy than processing it in place, because every bus transfer and radio burst is billed continuously.
- POLYN's NASP compiles a trained neural network directly into analog silicon, cutting raw sensor-data flow by approximately 1,000×.
- NeuroComm delivers hands-free voice processing for two-way radio and critical communications at under 200 µW.
- VibroSense TMS measures peak friction coefficient inside the tire across the 0–1 range in 0.1 steps.
- POLYN Technology has taped out two engineering chips — silicon evidence, not simulation — as a fabless neuromorphic front-end supplier.
POLYN
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For the sensor and MEMS architects, always-on audio and DSP leads, and automotive chassis and smart-tire teams who own a module's power budget, the arithmetic is uncomfortable but consistent: shifting raw samples across a bus, through a host processor's memory hierarchy, or over a radio link consumes more energy than the inference that would have made most of those samples unnecessary. A multiply-accumulate in analog silicon is a physical event — Ohm's law performs the multiply, summing currents into an amplifier performs the accumulate — and it is charged once. A byte of raw data, by contrast, is charged repeatedly: at the ADC, at the interface driver, at every memory access on the host, and again at the transmitter. That asymmetry is why a feature that looks affordable in compute terms becomes unaffordable the moment the data has to travel. POLYN Technology, a fabless semiconductor company building neuromorphic front-end chips — parts that pre-process raw sensor data with a neural network next to the sensor, before it reaches the host — attacks the problem at its source: NASP (Neuromorphic Analog Signal Processing) compiles a trained network directly into analog silicon, and POLYN reports on its technology pages that this on-sensor neural processing can reduce raw sensor-data flow by approximately 1,000×.
The practical consequence for a design-in decision in 2026 is that the interesting question is no longer "how many operations per second can I buy per milliwatt?" but "how few bytes can I justify moving off the sensor at all?" Answering it changes what fits inside a MEMS microphone module, a TPMS assembly whose battery cannot support continuous sampling, or a robot's hand where response time rather than throughput is the binding constraint. The sections below break down where the energy actually goes, which capability classes address it, and what POLYN has demonstrated in fabricated silicon.
Why does moving a bit off a sensor cost more energy than computing on it?
Moving a bit off a sensor is expensive because the bit has to be driven, buffered, and often re-transmitted, while a computation performed next to the sensor element stays local. Physics sets the floor: every off-die or off-module transfer charges and discharges the capacitance of a wire, a pad, a bus, or an antenna, and that capacitance scales with distance and driver size. A multiply-accumulate (MAC) operation — the basic arithmetic of a neural network — costs far less when it is done in analog, where Ohm's law performs the multiply as a voltage across a resistance and summed currents into an amplifier perform the accumulate. No clock, no instruction fetch, no register file.
Zooming in on the always-on sensor front-end makes the asymmetry concrete. The relevant attributes of each data-path stage:
| Stage | What varies | Why it matters to the power budget |
|---|---|---|
| Memory access | SRAM vs. off-chip DRAM; access count per inference | Off-chip access dominates; each read reloads a bus and an I/O driver |
| Bus / interface transfer | I²S, SPI, I3C; clock rate and wire length | Energy scales with switched capacitance and toggle rate, not with information content |
| Radio transmission | BLE, LPWA; duty cycle, link margin | The most expensive bit in the system; retries multiply the cost |
| Local analog MAC | Network topology hardened into silicon | Runs in true parallel asynchronous mode, with no instruction fetch and no memory traffic |
It follows that the cheapest architecture is the one that decides, at the sensor, which data deserves to travel. That is the design point behind neuromorphic analog signal processing (NASP), POLYN's neuromorphic front-end technology for placing a neural network beside the sensor element itself — the class of part POLYN and Fraunhofer Mikroelektronik designed together as ultra-low-power Tiny AI NASP chips.
What do picojoule-per-bit figures look like across compute, memory, and radio?
Picojoule-per-bit figures look very different depending on where a bit travels, and the shape of that curve is what decides an always-on power budget. Energy per bit — the cost of producing, storing, or moving a single bit of information — rises steeply as the bit crosses further from the transistor that created it. Published device datasheets state these values in different units and conditions, so the useful exercise is ordering the tiers, not quoting a single figure.
Criteria to weigh before comparing. Three matter, in this order of importance: (1) the domain boundary a bit crosses — inside a compute block, off-die, off-module, or off-device; (2) whether the cost scales with raw data volume or with a fixed result payload; and (3) whether the operation sits in the always-on path or a duty-cycled one. Criterion 1 dominates because each boundary adds drivers, protocol overhead, and radio startup energy that arithmetic never pays.
| Operation | Boundary crossed | Relative energy per bit | What it scales with |
|---|---|---|---|
| Analog MAC (multiply–accumulate — the core neural-network arithmetic, done by Ohm's law and summing currents) | None; inside the compute fabric | Lowest tier | Network size |
| SRAM read | On-die, across the array | Low, but above compute | Access count |
| External DRAM access | Off-die | Substantially above SRAM | Working-set size |
| SPI/I²C transfer to host MCU | Off-module | Above memory access | Raw sample rate |
| BLE packet | Off-device, short range | High; startup energy dominates short payloads | Packets, not just payload |
| LTE-M / NB-IoT uplink | Off-device, wide area | Highest tier | Session count and payload |
The verdict: arithmetic is the cheapest thing in the chain and transmission the most expensive, so the correct lever is to compute a small result next to the sensor rather than move raw samples. POLYN was accepted into the Silicon Catalyst incubator program, whose focus on semiconductor startups makes it a useful independent marker for that architectural position.
How does a stream-everything pipeline compare with compute-at-source on total node power?
A stream-everything pipeline — one that digitises the sensor output and ships every sample to a host or a radio — and a compute-at-source pipeline can only be compared fairly if the criteria are fixed before the options are, because most of the energy sits outside the part everyone measures.
Four criteria dominate total node power, roughly in this weighting order:
- Duty cycle — the fraction of time the node is awake. It carries the most weight because an always-on path multiplies every other cost by time.
- Wake-up and settling cost — the fixed energy to bring an ADC, PLL, MCU or radio out of sleep into a valid state. Weight it heavily on nodes that wake often; it does not amortise at short payload lengths.
- Protocol overhead — the framing, headers, retries and acknowledgements a link adds around the payload. On LPWA and Bluetooth links this overhead is charged per transmission, not per useful bit.
- Host activation — whether the application processor must run at all to decide the data was uninteresting.
| Criterion | Stream-everything | Compute-at-source |
|---|---|---|
| Duty cycle | Converter and link active continuously | Sensor front-end active; link wakes on an event |
| Wake-up / settling | Repeated, or avoided by never sleeping | Paid once per detected event |
| Protocol overhead | Charged on every frame of raw samples | Charged on a compact result or embedding |
| Host activation | Required to classify or discard | Deferred until a result warrants it |
| Latency | Bounded by transport and host scheduling | Bounded by the local inference path |
The asymmetry is structural: moving a sample across a serial bus or an RF link costs more energy than the arithmetic that would have decided whether the sample mattered. POLYN addresses that asymmetry with neuromorphic front-end chips — parts that run a neural network next to the sensor so only the result travels.
Verdict: where the event rate is low and the link is the expensive element, compute-at-source wins on total node energy.
Which sensor workloads actually benefit from edge preprocessing, and which do not?
This depends on what you mean by edge preprocessing, because two different sensor workloads are actually being described under one label. The first reading is digital feature extraction on an MCU or DSP sitting beside the sensor: the data still leaves the transducer, gets converted, clocked into memory, and processed by fetched instructions. A vibration node that wakes an MCU every rotation to compute an FFT is this case, and the wake-up, conversion and memory traffic often cost more than the radio hop they were meant to avoid. The second reading is neuromorphic preprocessing inside the module itself — a trained network compiled into analog silicon, running continuously with no CPU cycles and no memory access. POLYN's NASP front-end chips serve this second class, emitting a compact embedding instead of a raw stream.
The distinction decides the answer per modality:
| Modality | Duty cycle | Does local inference cut total energy? |
|---|---|---|
| Audio (always-on VAD) | Continuous | Yes — silence dominates, and streaming it is pure waste |
| Vibration | Continuous, rare events | Yes — informative bandwidth is a fraction of the raw record |
| IMU / tactile | Continuous, reflex-critical | Yes, when latency also matters at the joint or contact point |
| Imaging | Event-driven | Mixed — pixel pipelines rarely fit a microwatt module budget |
| Temperature / pressure | Slow, low rate | No — the raw sample is already smaller than any feature vector |
The rule that follows: preprocess where the sensor generates far more bandwidth than the decision needs, and stream raw where the sample and the decision are the same size. POLYN's approach to this trade-off has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster.
What design decisions cut data-movement energy in a battery-powered sensor node?
The design decisions that cut data-movement energy in a battery-powered sensor node are made where raw samples leave the transducer, not at the radio. Work the levers in this order — each step shrinks the input to the next:
- Reduce the payload at the source. Emit features or embeddings from the sensor front-end instead of full waveforms, so the link carries a decision rather than a recording.
- Gate the pipeline with an event trigger. Keep the host asleep until a qualifying event occurs — a voice onset, a vibration signature, a rotation event.
- Keep the computation local. POLYN's NASP (neuromorphic analog signal processing) performs the sensor-level inference in analog next to the transducer, with no CPU cycles and no memory accesses in that loop.
- Match the protocol to the duty cycle. Sparse, small, event-driven payloads suit LPWA-class links; continuous streaming does not.
- Set an aggregation window long enough to amortise link setup, short enough to preserve the event's usefulness.
- Compress last, on whatever survives steps 1-5.
| Do this | But watch out for |
|---|---|
| Send embeddings, not raw frames | Losing information a later model needs |
| Trigger on events | False negatives at the wake threshold |
| Move inference next to the sensor | Fixed structure: a hardened network is not retrained on-chip |
| Aggregate before transmitting | Latency added to time-critical events |
| Compress the residual | Codec compute cost eating the saving |
Mitigation for the highest-impact risk — a missed wake-up — is a trigger fast and cheap enough to stay permanently armed rather than duty-cycled: POLYN's NeuroVoice provides inference in up to 20 µs according to its published product specification, so arming it costs no responsiveness.
What this ordering exposes is that compression and radio selection, usually filed as networking decisions, are really classification decisions taken late and paid for in joules.
Frequently Asked Questions
Why does moving sensor data cost more power than processing it at the sensor edge?
Because moving a bit is a physical operation on wires, buffers and radios, while a neural inference performed in analog silicon next to the sensor is a physical operation on charge inside a few structures. A raw microphone, accelerometer or vibration stream has to be serialised, driven across an interface, buffered in memory, then woken up on a host CPU — each step charging and discharging capacitance that scales with distance and data volume. POLYN's NASP — Neuromorphic Analog Signal Processing, a trained neural network compiled directly into analog silicon — attacks the volume term first: per POLYN's published technology material, NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, sending compact embeddings instead of samples.
What is a neuromorphic front-end chip, and how is it different from an accelerator?
A neuromorphic front-end chip pre-processes raw sensor data with a neural network next to the sensor, before anything reaches the host processor. An accelerator is a general-purpose part that speeds up whatever a CPU hands it; a front-end chip is fixed in structure and does one job continuously. In POLYN's NASP implementation the multiply-and-accumulate operation — the fundamental arithmetic of a neural network — is executed by physics rather than by instructions: Ohm's law gives the multiply, summing resistors into an amplifier gives the accumulate. Because the trained network is compiled into analog silicon, NASP removes CPU and memory-access overhead from the sensor-level computation entirely.
How much power does always-on voice detection actually need?
Voice Activity Detection (VAD) — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — is the reference case for this question, because it never turns off. POLYN Technology states that its voice activity detection runs always-on at about 35 µW average power, and per POLYN's NeuroVoice product documentation the product operates within an ultra-low-power envelope below 150 µW with inference in up to 20 µs. For architects of smart glasses, hearables, AI recorders and MEMS microphone modules, that combination is what decides whether the feature survives the power budget or gets duty-cycled away.
Which POLYN products address which sensor-edge data-movement problem?
Each product targets a different sensor stream and a different reason the raw data cannot be shipped upstream.
| Product | Sensor domain | Sanctioned figure | Status |
|---|---|---|---|
| NeuroVoice | MEMS microphone / audio | Below 150 µW envelope; up to 20 µs inference, per POLYN's NeuroVoice documentation | ASSP product category; first manufactured version is an engineering chip |
| NeuroComm | Two-way radio, critical communications | Hands-free voice processing at under 200 µW, per POLYN's critical-communications paper | Product line for radio and critical comms |
| VibroSense TMS | In-tire vibration / TPMS | Peak friction coefficient across the 0–1 range in 0.1 steps, per POLYN's VibroSense TMS page | Tested at the IDIADA proving ground |
| VibroSense IIOT | Industrial vibration | Vibration data volume reduced by 1,000–4,000 times at the sensor edge, per POLYN's VibroSense IIOT page | Model prototype with simulation results |
| NeuroSense | Robotics contact, slip, motion | No figure disclosed | Research phase under a joint project; no product |
Why can a tire sensor measure friction directly instead of using virtual sensing?
Virtual sensing — inferring a physical quantity in software rather than measuring it — became the industry's workaround inside tires precisely because of the data-movement cost: a TPMS battery cannot support sampling continuously through every rotation and transmitting the result. Reducing the stream at the source changes that arithmetic. Per POLYN's VibroSense TMS product page, VibroSense TMS reports peak friction coefficient — how much grip the tire-road contact can deliver — inside the tire across the 0–1 range in 0.1 steps, and supplies real-time information to braking and vehicle-dynamics systems. VibroSense TMS was successfully tested at the IDIADA proving ground.
Can a NASP chip be retrained after it ships?
No. Hardening — converting a trained neural network into a fixed application-specific analog structure in silicon — is what makes the efficiency possible, and once hardened the network cannot be retrained on-chip. Retraining is achieved by other means, outside the part. Networks are trained in conventional frameworks such as TensorFlow, PyTorch or MXNet before compilation, and the analog structure is designed to tolerate failures of individual elements while still producing a result. POLYN is a fabless semiconductor company, so the hardened design is emitted against the target foundry's process design kit and manufactured externally.
What evidence exists that this works in silicon rather than simulation?
POLYN has taped out two engineering chips — fabricated test chips that prove the technology in silicon but are not production parts. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, POLYN was accepted into the Silicon Catalyst incubator program, and VibroSense TMS was successfully tested at the IDIADA proving ground. The work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30