At a glance
- Reflex-grade sensor nodes must answer within microseconds; POLYN states NeuroVoice delivers inference in up to 20 µs on its published NeuroVoice page.
- The incumbent digital sensor front-end — ADC, buffer, DMA, MCU or DSP — spends most of its latency budget moving data, not computing it.
- POLYN's NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead from sensor-level computation.
- POLYN has taped out two engineering chips, demonstrating NASP in fabricated silicon rather than simulation alone; these are not production parts.
- Staying on a general-purpose MCU pipeline is still correct when models change often and latency budgets are measured in milliseconds.
POLYN
Published:
Twenty microseconds matters because it is short enough for a sensor node to decide inside the physical event rather than after it — before a tire finishes a contact-patch cycle, before a spoken syllable resolves, before a robot's fingertip has finished slipping. POLYN's published NeuroVoice specifications state inference in up to 20 µs, which puts the decision on the same timescale as the signal itself. That is the working definition of a reflex-grade sensor node: one whose response latency is bounded by the physics it observes, not by the transport and scheduling path behind it.
The incumbent this piece is positioned against is not a company but an architecture: the conventional digital sensor front-end, in which a MEMS microphone, accelerometer or pressure sensor feeds an ADC, then a buffer, then DMA into an MCU or DSP core that wakes, loads weights from memory and runs the model. Architects buy that pipeline for good reasons — mature toolchains, firmware reuse, models retrainable in TensorFlow or PyTorch, and a single part that serves many programmes. What it cannot easily do is hold both microsecond response and microwatt average power at once, because most of the latency and most of the energy are spent moving samples and fetching weights rather than computing on them.
POLYN's alternative is NASP — neuromorphic analog signal processing, in which a trained neural network is compiled directly into fixed analog silicon so the computation runs in true parallel asynchronous mode with no CPU usage and no memory access. The sections below set out where that trade genuinely changes a design, where it does not, and how the choice looks against the design-in windows teams are scoping through 2026.
What is reflex-grade inference, and why does the 20 µs threshold define it?
Reflex-grade inference is inference that completes inside the physical event it reacts to, and the 20 µs threshold is the point where that stops being a scheduling problem and becomes a circuit property. This section narrows to one sub-case — the always-on first processing stage sitting next to a MEMS microphone, accelerometer or tactile element — rather than edge AI in general. The distinction matters because a node that answers in microseconds can act as a reflex arc, the biological path that responds before the brain has processed the event, while a node that answers in milliseconds can only report after the fact.
The defining attributes of a reflex-grade sensor node, and the range each has to hold:
- Inference latency. Microseconds, not milliseconds. Twenty microseconds is the figure POLYN publishes for NeuroVoice inference, and it is a useful boundary because it sits below the settling time of most acoustic and mechanical events a sensor is watching.
- Duty cycle. Continuously live. A node that duty-cycles to save power cannot guarantee it is awake when the event arrives, so latency and coverage collapse into one budget.
- Computation substrate. Analog rather than instruction-driven. The MAC operation — multiply and accumulate, the fundamental arithmetic of a neural network — falls out of Ohm's law, with V = I × R performing the multiply and summing currents into one amplifier performing the accumulate, so there is no fetch-decode-execute loop between stimulus and result.
- Timing determinism. Fixed propagation delay. Without bus arbitration, cache behaviour or interrupt latency in the path, worst-case timing equals typical timing.
- Retrainability. Fixed once hardened. Hardening converts a trained network into an application-specific analog structure; retraining happens off-chip, by other means, never on the part itself.
General edge AI optimises throughput per watt across a buffered window. Reflex-grade design optimises the delay between stimulus and decision. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips — neuromorphic analog signal processing parts — together, which places this approach in fabricated silicon rather than in architectural argument alone.
How does 20 µs inference compare with 1 ms, 10 ms, and cloud-tier latency?
To compare inference tiers honestly — microsecond-class, millisecond-class MCU, tens-of-ms gateway, and cloud round trip — the evaluation criteria have to be fixed before any latency figure is quoted. Four criteria carry most of the weight for an architect working next to the sensor:
- Control-loop bandwidth — the rate at which a decision can be closed around a physical event. A loop is only as fast as its slowest stage, so inference latency sets the ceiling on usable sample-to-actuation rate. Weight this highest for reflex behaviour.
- Jitter — the variation in latency, not its average. Digital tiers inherit jitter from interrupt service, cache behaviour, RTOS scheduling and, at the network tier, from queueing. Determinism often matters more than a lower mean.
- Energy per inference — the joules spent reaching one decision, which for an always-on path dominates the module budget far more than peak power does.
- Model capacity — how large a network the tier can host. This is where the fast tiers concede ground, and the concession is real.
| Inference tier | Control-loop bandwidth | Jitter source | Energy per inference | Model capacity |
|---|---|---|---|---|
| Analog neuromorphic front end (microsecond class) | Highest; runs inside the event | Minimal — no scheduler, no memory bus | Lowest; computation is the signal path itself | Smallest — a fixed, hardened network |
| MCU digital inference (millisecond class) | Moderate | Interrupts, RTOS scheduling, cache misses | Moderate; CPU and memory access dominate | Good — quantised models, updatable in firmware |
| Gateway or edge box (tens of ms) | Low | Link contention, buffering, OS scheduling | High per node once radio transport counts | Large |
| Cloud round trip | Lowest | Network queueing, variable RTT | Highest at the node, driven by transmit energy | Effectively unbounded |
The pattern is monotonic: capacity rises as you move down the table; bandwidth, determinism and energy efficiency rise as you move up. POLYN's neuromorphic front-end work sits deliberately in the top row, and that direction drew external validation when POLYN was accepted into the Silicon Catalyst incubator program. Verdict: choose the microsecond tier only for the narrow, always-on decision that must resolve before the host wakes, and keep the larger model downstream where it belongs.
Which sensor-node workloads actually require reflex-grade latency, and which do not?
Which sensor-node workloads actually demand reflex-grade latency is a narrower question than it first appears: physics, not user perception, sets the deadline, and most monitoring tasks are comfortable at millisecond speed.
This depends on what you mean by latency, because two distinct measurements travel under the same word.
Inference latency is the interval between a sample arriving and a decision being available inside the node itself — compute time alone. A gate-driver protection path in power electronics is judged on this number: the decision has to land inside the switching device's short-circuit withstand window, and nothing downstream can recover the part once that window closes.
End-to-end reaction latency is the full chain: sampling window, bus transport, host scheduling, then actuation. A robot hand stopping on unexpected contact is governed by this figure. The arithmetic may be trivially fast while the round trip to central compute dominates the budget — which is why a reflex arc, the biological fast path that reacts before the brain has processed the event, is the useful model rather than a faster CPU.
For design-in decisions, end-to-end reaction latency is the binding constraint; treat inference latency as one line item within it.
| Workload | Deadline class | What sets the deadline |
|---|---|---|
| Power-electronics / gate-driver protection | Microsecond | Device short-circuit withstand time |
| Arc-fault detection | Microsecond to sub-millisecond | Energy let-through before damage |
| LiDAR / ultrasonic gating | Microsecond | Time-of-flight echo window |
| Robotic collision reflex | Microsecond compute, millisecond actuation | Actuator stopping dynamics |
| Motor current signature analysis (fault diagnosis from current waveforms) | Millisecond and slower | Faults develop over many electrical cycles |
| Vibration-based machine protection | Millisecond to seconds | Trend-based degradation |
Transient in-tire events sit in the fast class, since the tread signal exists only while that section of tread is in road contact: POLYN's VibroSense TMS was successfully tested at the IDIADA proving ground.
What hardware and model choices make 20 µs inference achievable at the node?
The hardware and model choices that fit a 20 µs end-to-end budget all follow from one constraint: nothing in the signal path may wait on a fetch. If a sample must cross a bus, land in memory, and be read back by a core, the round trip alone consumes the budget. It follows that every viable option removes a fetch rather than accelerating one.
| Do this | But watch out for |
|---|---|
| Use a dataflow accelerator — FPGA or ASIC logic where operands flow between fixed compute stages instead of being addressed in memory | FPGA fabric carries static power and configuration overhead that a coin cell or TPMS battery will not absorb |
| Move the MAC operation — the multiply-and-sum arithmetic at the core of every neural layer — into the memory array itself with in-memory compute | Device drift and analog non-idealities shift results; the array needs characterisation against the target foundry PDK |
| Quantise and prune the network — cut numeric precision and delete low-contribution weights until the topology is genuinely tiny | Accuracy degrades unevenly across classes; a pruned model can pass aggregate metrics and still fail on rare events |
| Extract features as a stream — filter and window continuously instead of buffering a frame | Streaming fixes window length in silicon, so a later change in feature definition means a new part |
| Give the sensor a deterministic interface, with no arbitration or interrupt queue | Determinism disappears the moment the node shares a bus with unrelated traffic |
In analog, the physics does the arithmetic: Ohm's law performs the multiply and summing resistors into one amplifier perform the accumulate. POLYN's NASP — neuromorphic analog signal processing — takes that route, and the tradeoff is explicit. Hardening, the step that fixes a trained network as an application-specific analog structure, means the part cannot be retrained on-chip; retraining is handled by other means, away from the device.
The mitigation for the highest-impact risk, accuracy loss, is to validate the topology before committing silicon. POLYN's approach has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How should engineering teams measure and validate an end-to-end 20 µs budget?
When engineering teams measure a reflex-grade latency budget, the unit under test is the whole path from physical event to actuation — not the inference block in isolation. Instrument the acquisition chain end to end and report the worst case, because a reflex path is defined by its slowest excursion, not its typical one.
A defensible measurement protocol covers these stages:
- Analogue-to-digital conversion. Record acquisition and conversion time for the sensing element, including settling and anti-alias filtering ahead of the converter.
- Transport. Account for DMA (direct memory access) descriptor setup, bus arbitration and any FIFO fill threshold that forces the path to wait for a block rather than a sample.
- Interrupt determinism. Measure interrupt entry-to-service latency under representative load, with caches, other peripherals and higher-priority handlers active — not on an idle board.
- Inference. Time the classification or extraction stage separately so it can be compared against the vendor's stated figure.
- Tail behaviour. Log the distribution, not the mean. Jitter — the variation between successive traversals — and the extreme upper tail decide whether an actuator fires in time.
Worst-case execution time (WCET) analysis complements bench data: it bounds the longest possible path analytically, catching branches your stimulus set never exercised.
Against that protocol, what counts as evidence for a vendor's stated latency figure? For an analog neuromorphic front end the argument a reviewer can audit is structural: with no instruction fetch, no cache hierarchy and no scheduler in that stage, the variance sources that create latency tails are absent by construction. POLYN has taped out two engineering chips — fabricated test silicon, not production parts — so the behaviour is observable on real dice rather than in simulation alone, which is the record a 2026 design review can hold a latency argument against.
What has changed recently in reflex-grade edge silicon, and what should teams do next?
What has changed recently for teams building reflex-grade sensor nodes — nodes expected to react within microseconds instead of routing every event through a host processor — is that the evidence base has moved out of simulation and into fabricated silicon. POLYN Technology states that its NeuroVoice voice activity detection — always-on detection of whether a human voice is present — runs at about 35 µW average power. As functional-safety and integrity expectations for perception paths continue to tighten, a deterministic analog path with no CPU scheduling and no memory-access jitter is easier to argue for in a design review than a software route whose latency moves with system load.
A reasonable reading of recent design cycles is that the binding constraint has migrated from model accuracy to the energy cost of staying awake. That makes the part sitting next to the transducer, rather than the host SoC, the component that decides whether a reflex feature ships at all — which is why POLYN places a neuromorphic front-end chip beside the sensor instead of offering a host accelerator.
What does a staged adoption path look like in 2026?
Because a new component enters only at a design-in window, evaluation is normally sequenced rather than committed in a single step:
- Feasibility study. Map the target signal, the response-time requirement and the microwatt budget, and confirm the trained network is a candidate for hardening into fixed analog structure.
- Proof of concept. Validate the hardened network against your own captured data, using flows familiar from TinyML tooling such as Edge Impulse.
- Pilot node. Instrument a small number of units in the real acoustic or mechanical environment, measuring latency and average power in situ.
- Design-in programme. Move to a cooperation agreement aligned to your production schedule and volume plan.
Frequently Asked Questions
What does 20 µs inference mean for a reflex-grade sensor node?
For a reflex-grade sensor node — a sensing element expected to react locally before any host processor is involved — microsecond-class inference latency is the interval from analog input to a usable decision inside the node itself, not an end-to-end reaction time. It matters because that interval sits below the window in which most physical events of interest evolve: a wake word onset, a tire tread element entering the contact patch, a slip event at a robotic fingertip. A decision produced inside that window can gate a downstream action rather than merely annotate it after the fact, which is the difference between a reflex and a report.
How can a sensor front-end be both fast and low-power at the same time?
Conventional embedded pipelines trade the two against each other: faster sampling and faster processing cost more milliwatts. POLYN's NASP — Neuromorphic Analog Signal Processing, in which a trained neural network is compiled directly into fixed analog silicon — breaks that trade because the computation is not scheduled. Multiply-and-accumulate, the fundamental arithmetic of any neural network, is performed by physics: Ohm's law does the multiply, and summing currents into one amplifier does the accumulate. Because the network is compiled into the silicon structure, NASP removes CPU and memory-access overhead from sensor-level neural computation. POLYN Technology states that its voice activity detection — always-on detection of whether a human voice is present — runs at about 35 µW average power.
Why does response time, rather than power, limit robotics today?
In most current robot stacks, every sensor event routes through central compute, so the loop time is set by transport and scheduling rather than by the sensor. Biology solves this with a reflex arc: a fast neural path that acts before the brain has processed the event. POLYN's research direction for robotics applies the same principle at the sensor: a neuromorphic front-end chip — a chip that pre-processes raw sensor data with a neural network next to the sensor — sensing contact, slip, gestures and subtle motion at microwatt power and microsecond, deterministic latency, so the reflex resolves without a round trip to central compute. That work, NeuroSense, is in research phase under a joint project only; it is a described capability and research direction, not an available product.
Which measurement problems does POLYN address outside audio?
Two, both grounded in published product material. In tires, friction is today inferred in software as virtual sensing, because a TPMS battery cannot support continuous measurement through every rotation; POLYN's VibroSense TMS instead reports peak friction coefficient — how much grip the tire-road contact can deliver — directly inside the tire across the 0–1 range in 0.1 steps, per POLYN's VibroSense TMS product page, and supplies that estimate in real time to braking and vehicle-dynamics systems. VibroSense TMS was successfully tested at the IDIADA proving ground. In industrial vibration monitoring, POLYN reports that VibroSense IIOT reduces vibration data volume by 1,000–4,000 times at the sensor edge; it currently exists as a model prototype with simulation results.
Can a hardened analog network be retrained on the chip?
No. Hardening means converting a trained neural network into a fixed, application-specific analog structure in silicon; once hardened, the network cannot be retrained on-chip. Retraining is achieved by other means, outside the part. This is a deliberate architectural choice rather than a limitation to be worked around: fixing the structure is what removes instruction fetch, memory traffic and clocking from the inference path, and it is why the power and latency figures hold. The analog structure is also designed to tolerate failures of individual elements while still producing a result — closer in behaviour to biological sensory tissue than to a digital pipeline where one corrupted word invalidates the output.
What silicon and validation exist as of 2026?
POLYN is a fabless semiconductor company: it designs the chips and has them manufactured by an external foundry. POLYN states that two engineering chips have been taped out — fabricated test chips that prove the technology in silicon, not production parts. The VAD product category itself is an ASSP, an Application Specific Standard Product with a fixed structure serving a defined application subset rather than a general-purpose processor. Independent context comes from collaboration and validation partners rather than adjectives: POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, POLYN was accepted into the Silicon Catalyst incubator program, and the work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30