What Is NASP? Neural Networks Compiled Into Analog Silicon

At a glance

NASP is POLYN's neuromorphic analog signal processing: a trained neural network compiled directly into fixed analog silicon next to the sensor.
Compiling the network into analog removes CPU cycles and memory access from sensor-level inference, cutting both power draw and response time.
POLYN's voice activity detection runs always-on at about 35 µW average power, and NeuroVoice delivers inference in up to 20 µs.
POLYN has taped out two engineering chips, so the architecture is proven in fabricated silicon rather than in simulation alone.
NASP is a front-end layer that pre-processes sensor data; the incumbent MCU or DSP keeps everything downstream of it.

POLYN

Published: 2026-08-30

NASP — neuromorphic analog signal processing — is POLYN Technology's method of compiling an already-trained neural network directly into an analog silicon structure, so the inference runs as physics rather than as instructions on a processor. The incumbent this sits against is the general-purpose digital always-on path: the low-power MCU core or DSP block already designed into microphone modules, TPMS units and vibration nodes, bought to do wake-word gating, filtering, feature extraction and sensor pre-processing before anything reaches the host. That incumbent path works, and it is programmable — but every sample it touches costs clock cycles, memory accesses and the power those consume, which is why the always-on feature is so often duty-cycled, degraded or moved off the device entirely.

The mechanism is straightforward once stated in circuit terms. A neural network is built from MAC operations — multiply and accumulate, the fundamental arithmetic of every layer. In analog, Ohm's law performs the multiply, since a voltage across a resistance yields a current, and summing those currents into an amplifier performs the accumulate. Compiling a trained network into that fabric — a step POLYN calls hardening — fixes the topology and weights in the die itself, and the computation then runs in true parallel, asynchronous mode with no instruction fetch and no memory traffic. Because the network is hardened, it cannot be retrained on-chip; retraining is handled off-chip and a new structure is compiled. The measured consequence is what matters to a power budget: independent lab measurement puts POLYN's always-on voice activity detection at about 35 µW average power, and per POLYN's NeuroVoice product documentation the part delivers inference in up to 20 µs.

This is a neuromorphic front-end chip, not an accelerator and not a replacement for the host processor. It sits at the sensor, converts a raw analog stream into a compact result or embedding — POLYN states that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, per its published technology overview — and hands that to whatever MCU, SoC or radio the system already uses. The sections below cover where the digital always-on path runs out of headroom, how the analog approach compares with the alternatives an architect would realistically shortlist in 2026, what the current silicon maturity actually is, and when staying on the incumbent path is the correct engineering decision.

What is NASP, and what does it mean to compile a neural network into analog silicon?

NASP stands for neuromorphic analog signal processing, and to compile a neural network into analog silicon means exactly what it says: a network trained in a conventional framework such as TensorFlow or PyTorch is converted into a fixed arrangement of analog components — resistors, amplifiers, interconnect — rather than into instructions a processor executes. This section stays narrow on that one mechanism: what the compilation step produces in silicon, and which attributes of the resulting part an architect has to evaluate.

The arithmetic makes the fit obvious. A neural network is built from MAC operations — multiply and accumulate. In the analog domain, Ohm's law performs the multiply (V = I × R), and summing several resistors into a single amplifier performs the accumulate. The network therefore runs as a physical structure in true parallel, asynchronous mode: no clocked instruction fetch, no CPU cycles, no memory access for the sensor-level computation. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, so the approach exists as fabricated silicon rather than as a simulation result alone.

Which attributes define such a part?

Computation domain — analog, continuous-time. There is no data-conversion or instruction-execution overhead between the sensor and the inference.
Programmability — hardened. Hardening converts the trained network into a fixed application-specific structure; the part cannot be retrained on-chip, and retraining is handled by other means, off the device.
Product category — ASSP (Application Specific Standard Product): a fixed-structure chip serving a defined subset of applications, closer in spirit to an ASIC than to a general-purpose processor.
Silicon maturity — engineering chip: fabricated test silicon that proves the architecture, not a production part.
Manufacturing model — fabless. POLYN emits the design against a target foundry's PDK and has it manufactured externally.

How does the NASP compilation pipeline turn a trained model into a fabricated chip?

The NASP compilation pipeline starts with a conventionally trained model and ends in fabricated silicon. The flow is deterministic rather than exploratory, which is what makes it reviewable at a design-in gate — the stage at which an architect is still comparing approaches rather than committing a bill of materials.

What are the stages of the flow?

Train in a standard framework. The network is trained on the target sensor's data in TensorFlow, PyTorch or MXNet. No proprietary training environment is imposed on the customer's data science team.
Map topology to analog primitives. The trained graph is reduced to structures an analog fabric can realise, with layer shapes and dynamic range constrained to what the circuit can physically represent.
Harden the network. Hardening converts the trained model into a fixed, application-specific analog structure. It follows directly that the part cannot be retrained on-chip: a new model means a new hardened structure, and retraining is handled off-chip by other means.
Synthesise the circuit. Each MAC operation — multiply and accumulate, the base arithmetic of any neural network — becomes physics rather than instructions: Ohm's law performs the multiply, and summing resistors into one amplifier performs the accumulate.
Emit against the foundry PDK. POLYN is fabless, so the layout is generated against the target fab's process design kit and sent out for manufacture.
Tape out and characterise. The result is an engineering chip — fabricated test silicon proving the technology in a real process, not a production part.

POLYN was accepted into the Silicon Catalyst incubator program, which gives architects external context for this flow.

How does NASP compare with GPUs, TPUs, and digital NPUs on latency, power, and cost?

To compare NASP with GPUs, TPU-class tensor accelerators and digital NPUs fairly, the evaluation criteria have to be fixed first, because these architectures occupy different places in the system. A neuromorphic front-end chip — one that pre-processes raw sensor data next to the transducer, with the trained function existing as fixed analog structure rather than as code — is a sensor-edge part, not a general-purpose compute engine.

Four criteria decide the outcome for an always-on sensor node, weighted in this order:

Latency character. Whether the decision emerges from a continuous analog signal path or from sample–buffer–fetch–compute cycles through memory.
Average power in continuous operation. The always-on path sets the budget; efficiency per operation matters less than what the part draws while nothing is happening.
Integration cost. Die area and package cost beside a MEMS microphone or a TPMS module, plus how much raw data must leave the sensor at all.
Model flexibility. How easily the network changes after tape-out. A hardened structure is fixed at fabrication, so retraining is handled off-chip by other means.

Architecture	Typical position	Latency	Continuous power	Flexibility
GPU	Training, datacenter inference	High, batch-oriented	Watts and above	Fully reprogrammable
TPU-class accelerator	Server and high-end edge	Throughput-optimised	High for a sensor module	Reprogrammable
Digital NPU / MCU+DSP	Edge and embedded inference	Clock- and memory-bound	Manageable, usually duty-cycled	Firmware-updatable
Analog neuromorphic front end	Inside or beside the sensor	Continuous path, no memory access	Microwatt class	Fixed at tape-out

Verdict: programmable accelerators remain the right tools for training and for models that change often; the analog approach wins only where a stable, narrow function must run permanently at the sensor.

Which analog approaches are not NASP: how does it differ from in-memory computing, memristor crossbars, and photonic accelerators?

"Analog AI" is an umbrella label covering several distinct approaches, and NASP is only one of them. This depends on what you mean by analog computation: some designs move multiply-accumulate arithmetic into a memory array, some into new device physics, some into light. Neuromorphic analog signal processing takes a different route — the trained model becomes fixed circuit topology in standard CMOS, a step POLYN calls hardening, so inference runs in true parallel asynchronous mode with no CPU cycles and no memory access.

Approach	Where the computation lives	Distinguishing trait
Analog in-memory computing	Inside a memory array, weights stored as cell conductances	Data movement shrinks, but weights remain stored values that must be written, read and refreshed
Memristor crossbars	Resistive-switching devices arranged in a grid	Depends on a non-standard device technology and its programming behaviour
Photonic accelerators	Optical paths, using interference and modulation	The optical domain performs the linear algebra; electrical conversion sits at both ends
POLYN's NASP front-end	Fixed analog network in standard CMOS beside the sensor	Weights are physical circuit structure, not stored state; a front-end part, not a general-purpose accelerator

The clearest way to place these approaches side by side is the MAC operation — multiply and accumulate, the fundamental arithmetic of a neural network. In POLYN's analog structure, Ohm's law performs the multiply and summing currents into an amplifier performs the accumulate, so the topology itself, rather than a stored weight matrix, holds the trained model. That also means retraining happens off-chip and never on the hardened part — a deliberate trade of flexibility for power and latency. POLYN's work in this area has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.

What accuracy, noise, drift, and yield risks come with running neural networks in analog silicon?

Accuracy in an analog neural network is bounded by physics rather than by numerical precision: thermal and flicker noise in the devices, process variation (the spread between nominally identical transistors and resistors on the same wafer), and drift — the slow shift of an operating point with temperature and ageing. Each of these erodes the margin of a MAC operation, the multiply-and-accumulate that Ohm's law performs when a voltage is applied across a resistive weight and currents are summed into an amplifier.

Design action	But watch out for
Train with device noise and mismatch modelled, then harden the result into silicon	Corner models only cover what was simulated; an unmodelled temperature range reappears as accuracy loss in the field
Exploit the distributed analog structure, which is designed to tolerate failures of individual elements while still producing a result	Graceful degradation is not unlimited redundancy — it does not license skipping yield analysis or Monte Carlo sign-off
Fix the precision target at system level — a detection flag or coarse class tolerates far more analog error than fine-grained regression	Reusing the same hardened block for a higher-resolution task silently exceeds its error budget

You may also be wondering whether a hardened network can be corrected after fabrication. It cannot be retrained on-chip: hardening compiles the trained network into a fixed, application-specific analog structure, and retraining is achieved by other means, off-chip, before a new structure is emitted against the target foundry's PDK.

The highest-impact mitigation is scope discipline. Because inference completes within a very short decision window, error cannot be averaged away over long integration — so choose sensor-edge tasks whose output is a robust decision, and leave high-precision numeric work to the host processor downstream.

Which workloads and edge deployments actually fit a NASP-style analog inference chip?

Screening workloads for edge deployments should start before any silicon commitment, using four weighted criteria that decide whether an analog neuromorphic front-end — a chip that pre-processes raw sensor data next to the sensor, ahead of the host processor — earns its die area.

Duty cycle. How much of the time must the function be awake? The higher the residency, the more the always-on path dominates the module's energy budget. Weight this first.
Data-reduction ratio. Does the sensor emit a continuous raw stream while the system only wants a sparse decision or a small embedding? A wide gap here is the strongest single indicator of fit.
Latency budget. If the response must land before a host processor can be woken, scheduled and run, the reflex has to sit beside the sensor. Weight this second in robotics and vehicle-dynamics work.
Function stability. The network is hardened — fixed into an application-specific analog structure at manufacture — so on-chip retraining is not available; retraining is handled by other means. Workloads whose model must change in the field score poorly.

Against those criteria, the strong candidates are always-on voice activity detection in MEMS microphone modules, hearables and smart glasses; in-tire sensing, where the TPMS battery cannot support continuous sampling; and vibration-based predictive-maintenance nodes. In the audio case the always-on voice activity detection has been measured in an independent lab at about 35 µW average power — a figure that carries weight precisely because the function never sleeps.

The four criteria are screened together rather than in isolation. A workload that stays awake continuously, emits far more raw signal than the system wants to move, must answer before the host can be woken, and runs a function that will not change in the field scores well on all four. A workload that fails any one of them — particularly function stability — belongs on the programmable path instead.

Frequently Asked Questions

What does NASP stand for, and what does it actually do?

NASP stands for Neuromorphic Analog Signal Processing, POLYN's core technology: a trained neural network compiled directly into analog silicon so that inference runs as a fixed physical structure rather than as software on a processor. Because the network becomes circuitry, NASP removes CPU and memory-access overhead from the sensor-level neural-network computation, and the layers operate in true parallel, asynchronous mode. The resulting part is best described as a neuromorphic front-end chip — it pre-processes raw sensor data next to the sensor, before anything reaches the host processor. POLYN states that this on-sensor neural processing can reduce raw sensor-data flow by approximately 1,000×, because what leaves the chip is a compact embedding or a decision rather than a full waveform.

How does analog circuitry perform neural-network arithmetic?

Analog circuitry performs neural-network arithmetic by mapping the multiply-and-accumulate (MAC) operation — the fundamental sum-of-weighted-inputs step of any neural layer — onto physics instead of onto an instruction set. Ohm's law supplies the multiply, since current through a resistor is a voltage scaled by a conductance, and summing several resistors into one amplifier node supplies the accumulate. No clock cycle, no register file, and no weight fetch from memory is involved; the answer settles as the circuit settles. This is why the analog front-end approach is a natural fit for always-on sensing paths, where the energy cost of moving weights and samples around usually dominates the energy cost of the arithmetic itself.

Can a NASP chip be retrained after it has been hardened?

No — hardening is the step that converts a trained neural network into a fixed, application-specific analog structure in silicon, and once hardened the network cannot be retrained on the chip. Retraining is achieved by other means, outside the part: the model is trained and adapted in software, and a revised network is compiled into a new silicon structure. One useful consequence of the fixed analog structure is robustness — it is designed to tolerate failures of individual elements while still producing a result, in the way biological sensory tissue keeps functioning despite imperfect individual cells.

Which POLYN products are built on NASP, and how mature are they?

POLYN's product families built on NASP span audio, automotive and industrial sensing, and their maturity differs by product, so it is worth stating each precisely:

Product	What it does	Status
NeuroVoice	Always-on voice activity detection (VAD) and single-microphone voice extraction	ASSP product category; first manufactured version is an engineering chip
NeuroComm	Hands-free voice processing for two-way radio and critical communications	The same voice building blocks packaged for critical communications; published envelope under 200 µW
VibroSense TMS	Tire-road friction measured directly inside the tire, feeding braking and vehicle-dynamics systems	Tested at the IDIADA proving ground
VibroSense IIOT	Vibration data reduction for predictive-maintenance sensor nodes	Model prototype with simulation results; business development on hold
NeuroSense	Sensor-level reflex layer for robotics and physical AI	Research phase under a joint project; no product

For the audio path, POLYN reports NeuroVoice inference in up to 20 µs, and its always-on voice activity detection was measured independently in a lab at about 35 µW average power. VibroSense TMS reports peak friction coefficient — how much grip the tire-road contact can deliver — across the 0–1 range in 0.1 steps, per POLYN's product documentation for the part.

How much of this exists in fabricated silicon rather than simulation?

Fabricated silicon, not simulation alone, is the basis of POLYN's technology claim: as of 2026 the company has taped out two engineering chips. An engineering chip is a fabricated test chip that proves the technology in silicon but is not a production part, and the distinction matters when an architect is planning a design-in window. POLYN is fabless — it designs the circuits and has them manufactured by an external foundry against that foundry's process design kit. Independent context comes from publicly announced relationships: POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, POLYN was accepted into the Silicon Catalyst incubator program, and VibroSense TMS was successfully tested at the IDIADA proving ground. The work has also been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.

What intellectual property protects the NASP architecture?

The intellectual property behind NASP covers analog neuromorphic processing and related energy-efficiency and signal-processing techniques. For an evaluating architect, the practical relevance is less the count than the fact that the compiled-network method itself, not just a product implementation, is documented in public record.

About this article

POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30