At a glance
- Inference in up to 20 µs lets a sensor decide locally, before data reaches central compute — the electronic equivalent of a reflex arc.
- POLYN states NeuroVoice provides inference in up to 20 µs, with voice activity detection running always-on at about 35 µW average power.
- POLYN's NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead from sensor-level computation.
- POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together; POLYN was accepted into the Silicon Catalyst incubator program.
- Two engineering chips have been taped out — fabricated silicon, not production parts and not simulation-only claims.
POLYN
Published:
For robotics perception and physical-AI architects, microsecond-class inference enables something the conventional stack cannot provide: a decision made at the sensor, inside the interval between a physical event and the host processor's next scheduled look at the data. POLYN's published figure for NeuroVoice, its audio front end, is inference in up to 20 µs, and that latency class is the whole point — at microsecond scale, the sensor node stops being a data source that reports upstream and starts being a reflex arc, the fast biological path that reacts before the brain has finished processing the event. That is a different architectural role from an accelerator. Two boundaries should be stated up front, because they bound everything below: that published figure is NeuroVoice's audio-path specification, and POLYN has not published an equivalent number for contact, slip or vibration; and POLYN's robotics reflex layer, NeuroSense, has no product — it is in research under a joint project with a large Japanese company, so it describes a research direction rather than something available to design in. POLYN Technology is a fabless semiconductor company — it designs chips and has an external foundry manufacture them — working at the sensor edge rather than the datacenter end of the AI spectrum, and as of 2026 its neuromorphic analog signal processing approach exists in fabricated silicon: two engineering chips have been taped out, engineering parts rather than production parts. The sections below map the reflex requirement to capability classes, then to what POLYN has published and what remains research.
What does 20 µs inference actually mean inside a reflex-driven control loop?
Inference at microsecond scale means one narrowly defined thing, and that meaning is worth separating from the shorthand around "real-time AI." POLYN Technology publishes inference in up to 20 µs for NeuroVoice, its audio front end, and the company binds that figure to that product and that signal class. POLYN has not published a latency figure for other signal classes, so the number cannot be carried across to contact, slip or vibration.
A reflex-driven system is one in which the reaction must complete before the physical event has finished developing: a gripper correcting before slip propagates, a radio front end waking before the first syllable is lost. In that class of loop, the compute stage earns its place only when it is small relative to the mechanical time constant it is trying to beat.
| Attribute | Range or behaviour | Why an architect cares |
|---|---|---|
| Published latency figure | POLYN publishes inference in up to 20 µs for NeuroVoice | The number is bound to one product and one signal class, audio |
| Sources of scheduling variance | Per POLYN's description of NASP: no instruction set and no memory access during computation | A path that fetches nothing leaves cache, bus and weight-load behaviour outside it |
| Execution model | Fully parallel and asynchronous, per POLYN's account of the architecture | Layers settle together rather than being dispatched as scheduled work |
| Placement | At the sensor, ahead of the host processor | Avoids serialising raw data across a link before any decision exists |
The mechanism is architectural: a trained network is compiled directly into fixed analog silicon, so multiply-accumulate — the core arithmetic of a neural network — happens as current summing rather than as scheduled instructions. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, which places the architecture in fabricated silicon rather than in simulation alone.
Which reflex-driven systems break at millisecond latency but work at 20 µs?
Reflex-driven systems break at millisecond latency whenever the physical event arrives and resolves before a host processor can be woken, handed the data over a bus, and scheduled. A reflex arc — the fast biological path that acts before the brain has finished interpreting the event — is the correct model here. When the decision must be made inside the event itself, inference next to the sensor is the only placement that works.
The table below is deliberately limited to the signal classes POLYN actually addresses, and each carries a different maturity. NeuroVoice is silicon; VibroSense TMS has been tested at a proving ground; the robotics reflex layer, NeuroSense, is a research project with no product behind it.
| Signal class | The reflex event | What fails at millisecond latency |
|---|---|---|
| Always-on voice interfaces (NeuroVoice) | Onset of speech | The wake decision lands after the first syllable is already lost |
| Robotic contact and manipulation (NeuroSense — research stage, no product) | Slip, grasp, unexpected collision | Force is applied before the hand can release |
| Tire and vehicle dynamics (VibroSense TMS) | Loss of grip at the contact patch | The braking or vehicle-dynamics command arrives too late |
Three attributes decide whether a design belongs in this class:
- Event timescale. If the event completes faster than a host round trip, no amount of host compute recovers it.
- Energy posture. A permanently-on path is judged in microwatts rather than milliwatts. Battery-bound nodes such as tire electronics or hearables cannot pay a milliwatt-class always-on budget at all.
- Placement — in-sensor, in-module, or central compute. Only in-sensor placement removes bus transfer and wake-up from the latency path.
POLYN's admission into the Silicon Catalyst incubator program reflects that this placement problem is treated as a semiconductor-architecture problem, not a software-scheduling one.
How does a 20 µs budget compare with 1 ms and 10 ms inference budgets?
Before comparing budgets, fix the criteria: a microsecond, millisecond or ten-millisecond figure only means something once you decide what it is being spent on. Inference latency here means the interval between a physical event reaching the sensor and a usable decision existing somewhere in the system. Three criteria decide which tier an architect actually needs, weighted in this order:
- Position of the decision relative to the event. Can the system still act while the event is happening, or only afterwards? This dominates every other consideration in a reflex-driven design.
- Duty cycle and energy posture. A path that must stay awake permanently is judged on average power, not peak throughput; a path that wakes on demand is judged on wake-up cost.
- Where the computation physically sits. Latency is largely a placement question — at the sensor, on a local MCU, or across a bus to central compute.
| Budget tier | Decision timing | Typical placement | Energy posture |
|---|---|---|---|
| Microsecond class | Acts within the event itself; reflex-class response | Neuromorphic front-end chip beside the sensor | Sized for permanently-on operation |
| Millisecond class | Acts after the event has developed; cycle-level control | Local MCU or DSP block | Wake-and-process, duty-cycled |
| Tens of milliseconds | Acts after the event has completed; supervisory correction | Central compute across a bus | Peak-power dominated |
The gap matters most where the physical process will not wait. Inside a rotating tire, contact-patch events pass before a supervisory loop could report them — which is why POLYN measures friction inside the tire with VibroSense TMS, successfully tested at the IDIADA proving ground, rather than reconstructing it downstream. The verdict: millisecond budgets suit correction; only the microsecond tier supports reflex.
Why do conventional GPU and CPU pipelines struggle to hit microsecond determinism?
A conventional GPU or CPU pipeline is built to maximise average throughput, not to bound worst-case response, and that design goal is exactly what makes microsecond determinism hard. Determinism here means a fixed, provable upper bound on the time from a sensor event to a decision; jitter is the variation around it. In a stored-program machine, that variation is structural, not a tuning defect.
The usual contributors stack up along the path:
- Bus transfer — moving a buffer across PCIe adds a queued, arbitrated hop before computation begins.
- Kernel launch overhead — the fixed cost of dispatching work to an accelerator, paid on every invocation regardless of payload size.
- OS scheduling — preemption, interrupt coalescing and timer granularity insert delays no application can predict.
- Batching — accumulating samples to keep utilisation high trades latency for efficiency by construction.
- Memory hierarchy — a cache miss falling through to DRAM costs whatever other code happened to evict.
- Managed runtimes and network stacks — garbage collection pauses and protocol buffering add rare but large excursions.
It follows that if a reflex loop must close within microseconds, no stage in it may have an unbounded tail. This means the meaningful metric is the far tail of the latency distribution, not the mean, because a reflex that misses rarely is still a reflex the system cannot trust. POLYN addresses this by placing the computation in the sensor path itself rather than dispatching it downstream; the approach has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
| Do this | But watch out for |
|---|---|
| Measure the tail, not the average | Short benchmark runs hide the rare excursions that matter |
| Pin threads and disable frequency scaling | Thermal headroom and throughput both drop |
| Reduce batch size toward one | Utilisation collapses and energy per inference rises |
| Move the decision next to the sensor | The function is fixed at design time, so the requirement must be settled early |
Highest-impact mitigation: specify the latency budget as a tail bound before architecture selection, so the worst case is a design input rather than a late discovery.
What hardware and model design choices make 20 µs inference achievable?
Scoping this narrowly: the hardware and model design choices below apply to a single always-on inference path sitting next to a sensor, not to a general-purpose edge accelerator. At microsecond scale the latency budget is dominated by data movement and control overhead rather than by arithmetic, so nearly every useful design move shortens or deletes a data path.
| Design move | Why it buys latency | But watch out for |
|---|---|---|
| Keep all weights resident on-chip | Removes external memory fetch from the critical path | A hard capacity ceiling — an oversized network does not degrade gracefully, it simply does not fit |
| Quantize and prune before committing to silicon | Fewer MAC operations (multiply-accumulate, the basic arithmetic of a neural network) and shorter routing | Accuracy must be re-validated after compression, never assumed |
| Use tiny MLPs or small 1-D CNNs | A single feed-forward pass gives a bounded worst case | The task must be narrowed — voice activity detection, not transcription |
| Emit a streaming dataflow mapping with HLS toolchains such as hls4ml or FINN | Replaces fetch-decode-execute with a pipeline | FPGA static power; an ASIC removes it but adds NRE and a design-in window |
| Place inference sensor-adjacent rather than across a link | Even a deterministic fieldbus adds a round trip | Integration effort shifts into the module, where die area and microwatts are scarce |
POLYN's NeuroVoice takes this further by compiling the trained network directly into analog structure, where Ohm's law performs the multiply and summed currents into an amplifier perform the accumulate — leaving no CPU cycles and no memory accesses in the loop. That compiled-silicon mechanism, rather than a faster clock, is what the company's published audio-path latency rests on.
A reasonable reading is that microsecond latency is bought less by raw speed than by scope discipline. The highest-impact risk follows directly: a hardened network cannot be retrained on-chip, so freeze the task definition and complete retraining off-chip before design-in.
Frequently Asked Questions
What does 20 µs inference enable in reflex-driven systems?
A microsecond-class inference budget lets a reflex-driven system act on a sensor event before the host processor has been woken, let alone scheduled. POLYN's published audio-path figure for NeuroVoice, cited earlier in this article, is short enough that the decision — voice present — is available inside the sampling window rather than one frame later. Applying the same principle to non-audio reflex events such as contact and slip is a research direction for POLYN rather than a published specification. In practice the pattern collapses the classic architecture in which every raw sample travels to central compute and the answer travels back. The reflex arc, the biological fast path that responds before the brain has processed the event, is the design model: local decision first, central reasoning afterwards.
How can analog silicon hit that latency without a CPU?
NASP — neuromorphic analog signal processing — compiles a trained neural network directly into fixed analog structures, so the multiply-and-accumulate arithmetic of the network is executed by physics rather than by instructions. Ohm's law performs the multiply, summing resistors into an amplifier performs the accumulate, and the layers settle in true parallel asynchronous mode. Because the trained network is compiled into silicon, this approach removes CPU and memory-access overhead from the sensor-level neural computation entirely. There is no fetch, no weight load, and no instruction set in the path.
Can the network be retrained on the chip after fabrication?
No. Hardening — converting a trained network into a fixed application-specific analog structure — is a one-way step, and the resulting part cannot be retrained on-chip. Retraining is achieved by other means, outside the device, with an updated network compiled into a subsequent design. The upside of that fixity is robustness: the analog structure is designed to tolerate failures of individual elements while still producing a result, in the way biological sensory tissue degrades gracefully rather than failing outright.
What power envelope does this latency come with?
Low latency and low power are not traded against each other here. POLYN Technology states that its always-on voice activity detection — continuous detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power, and its published NeuroVoice material places the product envelope below 150 µW. For hands-free two-way radio and critical communications, POLYN's NeuroComm documentation specifies voice processing at under 200 µW.
How does the same reflex principle apply outside audio?
The mechanism transfers wherever a sensor produces more data than the system wants to move, though the maturity differs sharply by product. POLYN's technology documentation states that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, converting waveforms into compact embeddings at the source. In automotive use, POLYN's VibroSense TMS specification describes reporting peak friction coefficient — the grip available at the tire-road contact — across the 0–1 range in 0.1 steps, measured inside the tire and supplied in real time to braking and vehicle-dynamics systems rather than inferred by virtual sensing in software. For robotics, the corresponding reflex layer, NeuroSense, is not an available product: it is in research phase under a joint project only, and no latency or power specification has been published for it.
What is the current maturity of the silicon in 2026?
POLYN is a fabless semiconductor company, meaning it designs the parts and has them manufactured at an external foundry. Two engineering chips have been taped out — fabricated test devices that prove the architecture in silicon but are not production parts. The voice activity detection product category itself is an ASSP, an application-specific standard product with a fixed structure serving a defined set of applications, though the first manufactured version of it remains an engineering chip. The robotics reflex layer remains a research project rather than silicon a team can specify. Engagement begins with a proof of concept and technical evaluation rather than an off-the-shelf order.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30