At a glance
- NeuroVoice operates within an ultra-low-power product envelope below 150 µW, per POLYN's published product page, making an always-on voice path affordable in a tight BOM.
- POLYN Technology states its voice activity detection runs always-on at about 35 µW average power, measured as an average across the always-on duty cycle.
- NeuroVoice provides inference in up to 20 µs, per POLYN's product documentation, so responsiveness is not traded away for power.
- NASP compiles a trained neural network directly into analog silicon, removing CPU cycles and memory access from sensor-level computation.
- POLYN has taped out two engineering chips — not production parts — proving the architecture in fabricated silicon rather than simulation alone.
POLYN
Published:
Sizing a sub-150 µW voice front-end into a tight bill of materials starts with one budget line: the always-on listening path. NeuroVoice operates within an ultra-low-power product envelope below 150 µW, per POLYN's published product page. Within that envelope, an independent lab measurement puts POLYN Technology's voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — at about 35 µW average power. That envelope is what makes a permanently listening feature survive the BOM review instead of being duty-cycled, cut, or pushed to the cloud, because the power a front-end draws while nothing is happening is the number that dominates battery life in a device that must listen all day.
The second number architects check is latency, since the usual trade is that saving power costs responsiveness. NeuroVoice provides inference in up to 20 µs according to POLYN's product documentation, which means the wake decision arrives well inside the window a downstream MCU or SoC needs to spin up its audio pipeline. The mechanism behind both figures is NASP — neuromorphic analog signal processing, POLYN's core technology, in which a trained neural network is compiled directly into analog silicon so the computation runs in true parallel asynchronous mode with no CPU usage and no memory access. In analog, Ohm's law performs the multiply and a summing node performs the accumulate, so the MAC operation that defines a neural network costs almost nothing to execute. POLYN is a fabless semiconductor company, meaning it designs the silicon and has an external foundry manufacture it, and it has taped out two engineering chips — fabricated test devices that prove the technology in silicon, not production parts.
What follows is a practical sizing exercise for principal architects and product owners weighing a neuromorphic front-end chip against the rest of the BOM in 2026: where the microwatts and board area actually go, which outcomes the part buys you, how the design-in and evaluation path works, and — just as important — the cases where this approach is not the right fit.
What exactly is a sub-150 µW voice front-end, and which blocks does it contain?
A sub-150 µW voice front-end is exactly the chain of blocks that sits between a MEMS microphone and the host processor, and that must keep the voice path alive continuously without waking anything expensive. Everything in that chain is defined by which power domain it lives in — always-on, or duty-cycled and normally dark.
| Block | Function | Power domain | Why the architect cares |
|---|---|---|---|
| MEMS microphone | Micro-machined acoustic transducer converting pressure to an electrical signal | Always-on | Sets the noise floor and the sensitivity the rest of the chain inherits |
| PDM/PCM interface | Pulse-density modulation (single-bit oversampled stream) or pulse-code modulation (multi-bit samples) transport | Always-on | Determines clock rate and I/O toggling, a real share of the budget |
| Analog front-end (AFE) | Bias, gain and anti-alias filtering before conversion | Always-on | Where analog-domain processing can begin before any digitisation cost |
| Low-power codec | Coder-decoder converting between analog and digital audio | Duty-cycled | Only needs to run when speech is actually present |
| Voice activity detection (VAD) | Always-on detection of whether a human voice is present | Always-on | The gatekeeper; its average power effectively is the standby power |
| Wake-word / keyword spotting (KWS) engine | Recognises a specific trigger phrase | Duty-cycled, VAD-gated | Costly per inference, so it must be enabled rarely |
The boundary between those two domains is the whole design. If the detection stage draws more than the always-on budget allows, the feature gets duty-cycled or removed. POLYN works that boundary in the analog domain, where a multiply-and-accumulate (MAC) operation — the fundamental arithmetic of a neural network — falls out of Ohm's law: resistance performs the multiply, and summed currents into one amplifier perform the accumulate. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together. As a product category, a fixed-structure VAD part of this kind is an ASSP: an application-specific standard product, not a general-purpose processor.
How do you split a 150 µW budget across the microphone, interface, and always-on wake-word engine?
Splitting an always-on audio power budget across the microphone, the digital interface, and the wake-word engine starts by ranking each block by how much of the time it actually draws current, not by its peak figure. Four of the five consumers below run continuously, which is why a datasheet peak number tells you almost nothing about the average.
- MEMS microphone bias and analog current — a fixed, permanent draw. It scales with the mic's supply rail and its sensitivity grade, not with duty cycle.
- PDM clock and interface toggling — dynamic power rises with clock frequency and with the square of the supply voltage, so a lower PDM rate and a scaled rail move this block more than any other single choice.
- Voice activity detection (VAD) gate — always-on detection of whether a human voice is present, used to keep the rest of the device asleep until someone speaks. This is the block that must never be duty-cycled.
- Keyword-spotting inference — cheap on average only if the VAD gate in front of it is accurate; false wakes multiply its effective duty cycle.
- Static leakage — unaffected by duty cycling and worse at elevated junction temperature.
| Do this | But watch out for |
|---|---|
| Drop the PDM clock and sample rate to the minimum the wake model tolerates | Aliasing and lost high-frequency phonemes raise the false-reject rate |
| Scale the supply rail down | Analog headroom in the mic front-end collapses before the digital side does |
| Gate the inference engine behind VAD | Every false wake charges the full inference cost to the average |
| Budget leakage explicitly | It survives every sleep mode you add |
The most common overrun is a wake engine implemented on a general-purpose MCU, where CPU cycles and memory access dominate. POLYN attacks that term directly by compiling the trained network into analog silicon, which removes CPU and memory-access overhead from the sensor-level computation. Separately, as third-party validation of the company rather than of that mechanism, POLYN was accepted into the Silicon Catalyst incubator program.
Which front-end architecture fits a tight BOM: analog MEMS plus external ADC, PDM digital mic, or a microphone with integrated VAD?
Which voice front-end architecture fits a cost-constrained battery design depends almost entirely on where the always-on listening burden lands — in the codec, in the host MCU, or beside the microphone itself. Weigh the criteria in this order before looking at any part number:
- Always-on power — the current drawn while nothing is being said. This dominates battery life and should be weighted highest.
- Part count and board area — every discrete raises BOM cost, placement cost and failure modes.
- Wake latency — the delay between speech onset and a valid wake decision. Too slow and the first syllable is lost.
- SNR and AOP — signal-to-noise ratio and acoustic overload point, the microphone's usable dynamic range between whisper and shout.
- Firmware effort — DSP tuning, threshold calibration and requalification after every model change.
- Supply-chain risk — single-source parts and long-lead analog components.
| Architecture | Always-on power | Part count | Wake latency | SNR / AOP | Firmware effort | Supply risk |
|---|---|---|---|---|---|---|
| Analog MEMS + external ADC | Highest — ADC and host stay biased | Highest: mic, ADC, passives, host | Moderate, set by conversion and buffering | Best control; AOP set by your own front-end | Heavy: full DSP chain in-house | Multi-vendor, several lead times |
| PDM digital microphone into MCU | Moderate — decimation runs on the host | Two active parts | Depends on host wake and decimation depth | Fixed by the microphone datasheet | Moderate: decimation, filtering, thresholds | Single mic vendor, common package |
| Microphone with integrated VAD (always-on companion die) | Lowest — host stays asleep until voice is detected | Fewest: mic plus one companion die | Lowest; the decision is made before the host wakes | Set by the microphone; the detector adds no conversion stage | Lightest: the network is hardened in silicon | New die to qualify; design-in required |
For a tight BOM on a coin cell, pairing the microphone with an always-on voice detection companion — the category POLYN addresses in NeuroVoice — is the only option that removes the host from the idle path entirely.
What does each architecture add to unit BOM cost, board area, and passive count?
When a design already has its bill of materials committed, each architecture adds a different set of line items, and what it adds is rarely just the silicon. Weigh the options on these criteria, in roughly this order of impact on landed cost:
- Rail count and regulation — every additional supply voltage means an LDO (low-dropout regulator) or buck converter plus its own decoupling and bias passives.
- Clock source — a crystal is a placed part with load capacitors; an on-die RC oscillator removes both, at the cost of frequency precision.
- Interconnect — a remote microphone needs a connector and flex cable, which are often the most expensive non-silicon items in a compact wearable.
- Board area — measured not by die footprint but by keep-out, passives and routing channels around it.
- Assembly and test — placement count, reflow profiles and end-of-line test time all scale with part count.
| Criterion | Host MCU stays awake | Dedicated DSP co-processor | Analog neural front-end at the microphone |
|---|---|---|---|
| Rails | Existing rail, but at duty-cycled current | Usually a second rail | Fits the microphone's existing supply domain |
| Clock | Host crystal | Often its own crystal | RC-class timing adequate; no crystal placement |
| Interconnect | Long mic trace or flex to host | Flex to host retained | Local to the MEMS microphone; short trace |
| Passives | Minimal added | Decoupling and bias per device | Small decoupling set |
| Assembly | No new placements | Added placements and test time | One added placement, near the sensor |
The levers that reduce cost at volume are consolidation, not negotiation: collapse rails, delete the crystal, shorten the flex, and move the always-on decision next to the sensor so the host connection carries events rather than continuous audio. Engineers evaluating POLYN's NASP approach at this level of detail can follow the technical write-ups in EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and a tinyML Talks session.
How do you keep wake-word accuracy and false-accept rates acceptable at these power levels?
You keep wake-word accuracy defensible at these power levels by splitting the decision rather than weakening it. The always-on stage answers only one question — is human speech present? — and it follows that this stage does not need the sample rate, bit depth, or dynamic range a full keyword-spotting (KWS) decoder needs. Accuracy is then budgeted where it is actually consumed, in the second stage, which runs only after the first stage has already discarded silence and non-speech. POLYN's NeuroVoice is built around that split: its voice activity detection runs always-on and wakes the rest of the system only when a human voice is present.
| Do this | But watch out for |
|---|---|
| Cut sample rate and bit depth in the always-on stage | Quantisation noise approaching the microphone's self-noise floor, which erodes signal-to-noise ratio for distant talkers |
| Bias the first stage toward false accepts (rarely miss speech) | Every false accept wakes the downstream stage, so the power saving degrades in a noisy room |
| Bias the second stage toward false rejects (rarely fire wrongly) | Far-field and reverberant utterances arriving weakest are the first to be rejected |
| Validate on recorded corpora before silicon selection | Corpora rarely capture the port geometry, sealing, and resonances of your actual enclosure |
| Check behaviour near the acoustic overload point — the sound-pressure level at which the MEMS microphone begins to distort | Clipped consonants confuse a detector that trained only on well-levelled speech |
A less obvious consequence of the cascade: the constraint that limits accuracy is often not detector quality but how much of the utterance survives the handover between the two stages, which is a property of the gating architecture rather than of either detector taken on its own.
Highest-impact mitigation: run the final false-accept versus false-reject sweep with the microphone mounted in the production enclosure, not on a bench fixture.
Frequently Asked Questions
What does a sub-150 µW voice front-end actually include?
A voice front-end in this class covers the always-on listening path: the analog interface to a MEMS microphone (a microelectromechanical-systems microphone, the standard capacitive part in consumer devices), the neural processing that decides whether human speech is present, and the wake signal handed to the host processor. NeuroVoice operates within an ultra-low-power product envelope below 150 µW, per POLYN's published NeuroVoice product information. Inside that envelope, an independent lab measurement puts POLYN Technology's voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — at about 35 µW average power.
How does NASP get the power down without slowing response time?
NASP, POLYN's neuromorphic analog signal processing, compiles a trained neural network directly into analog silicon rather than executing it as instructions on a processor. The multiply-and-accumulate operation that underpins every neural network — multiply, then sum — falls out of physics in the analog domain: Ohm's law performs the multiply, and summing currents into a single amplifier performs the accumulate. Because the network is hardened into fixed structure, NASP removes CPU and memory-access overhead from sensor-level neural computation, so the usual trade between faster processing and higher power does not apply in the same way. NeuroVoice provides inference in up to 20 µs, per POLYN's NeuroVoice product page.
Which line items on the bill of materials does a neuromorphic front-end chip change?
A neuromorphic front-end chip — a part that pre-processes raw sensor data with a neural network next to the sensor, before that data reaches the host — shifts cost between BOM lines rather than simply adding one.
| BOM element | Effect of adding an always-on analog front-end |
|---|---|
| Host MCU / SoC | Can stay asleep until a wake event arrives, so duty cycle rather than peak MIPS drives selection |
| Battery / PMIC | Standby drain is dominated by the listening path; a lower always-on figure relaxes cell sizing |
| Memory | The trained network lives in fixed analog structure, so no weight-storage or fetch traffic at the sensor |
| Data interface | NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, per POLYN's technology documentation |
Can the chip be retrained in the field after design-in?
No. Hardening — converting a trained neural network into a fixed application-specific analog structure — is one-way: once the network is in silicon it cannot be retrained on-chip. Retraining is achieved by other means, outside the part. Architects should treat the hardened network as they would any fixed-function block, and plan the training and validation cycle before tape-out rather than assuming field updates to the model itself.
What silicon and independent validation exist today?
POLYN Technology has taped out two engineering chips — fabricated test chips that prove the technology in silicon but are not production parts. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and POLYN was accepted into the Silicon Catalyst incubator program. The work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
When is this front-end approach the wrong fit?
It is the wrong fit when the workload is general-purpose or expected to change after manufacture: an ASSP — an application-specific standard product with fixed structure, the standard category for VAD chips — serves a defined subset of applications, not arbitrary models. It is also the wrong fit for a team that needs a catalogue part it can order today, because POLYN does not sell off the shelf; engagement in 2026 runs through business development, typically a proof of concept or cooperation agreement ahead of a design-in programme. Programmes needing a general-purpose applications processor, or datacenter-scale model inference, sit at the opposite end of the spectrum from sensor-edge analog processing.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30