At a glance
- Always-on sensing power budgets fail when architects average the wake path instead of counting duty cycle, wake-ups and host cost.
- POLYN's voice activity detection runs always-on at about 35 µW average power, per the company's own claim.
- NeuroVoice operates within an ultra-low-power product envelope below 150 µW, keeping the listening path inside a module budget.
- Moving raw data instead of compressing it at the sensor is the second most common budgeting error.
- POLYN's NASP compiles a trained neural network into analog silicon, removing CPU and memory-access overhead from sensor-level inference.
POLYN
Published:
The most expensive mistake in an always-on sensing power budget is counting only the inference block and ignoring everything the wake path drags behind it: the ADC, the data bus, the host processor that must boot to decide the event was a false alarm, and the duty cycle that turns a modest active current into an unaffordable average. Budget the whole chain, in average microwatts over a realistic activity profile, and budget it before the architecture is frozen — not after. The second recurring error is treating raw sensor data as something to move rather than something to reduce at the source; POLYN's NASP (Neuromorphic Analog Signal Processing, in which a trained neural network is compiled directly into analog silicon) can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, according to POLYN Technology's published technology description.
Those two errors compound. An architect who under-counts the wake path usually compensates by duty-cycling the sensor, which trades away exactly the responsiveness the always-on feature existed to provide — and an architect who moves raw samples to a host for classification pays for that transport twice, once in bus energy and once in host wake-ups. This article walks through the budgeting mistakes that recur across MEMS microphone modules, hearables and smart glasses, TPMS and smart-tire electronics, and robotic sensing nodes, and shows what the numbers look like when the neural network sits in analog silicon next to the sensor instead of in software behind it. POLYN's voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power in independent lab measurement, which is the order of magnitude a permanently listening product has to hit in 2026 to survive a battery review.
What are the most common mistakes when budgeting always-on sensing power?
The most common mistakes in always-on sensing power budgets are accounting errors, not physics errors — the scope here is narrow: the microwatt-class path that must stay awake permanently in a battery-powered device, not the burst path that runs after an event is confirmed. Four recurring errors dominate.
Mistake 1 — budgeting the inference, not the listening. The energy that matters is what the device burns during the long silent interval, not during the rare detection.
Mistake 2 — counting MACs and ignoring data movement. A MAC operation (multiply-accumulate, the fundamental arithmetic of a neural network) is cheap next to the bus traffic, memory accesses and CPU wake-ups needed to feed it. On a conventional digital microcontroller path, that overhead can dominate the arithmetic it serves.
Mistake 3 — treating duty-cycling as a saving. Sampling intermittently lowers average current by discarding time, and events that fall in the gaps are simply not seen.
Mistake 4 — assuming module headroom exists. Inside a MEMS microphone or a TPMS module, both microwatts and die area are already allocated.
| Do this | But watch out for |
|---|---|
| Budget the silent-listening state separately from the detection burst | Averaged datasheet figures that hide the always-on floor |
| Move detection next to the sensor | Front-end silicon that adds its own controller and memory |
| Duty-cycle only non-critical channels | Missed transients and degraded response time |
| Reserve area and current at architecture stage | Design-in windows that close before the budget is revisited |
The highest-impact mitigation is structural: remove the CPU and memory-access overhead from the sensor-level computation entirely by compiling the trained network directly into analog silicon, which is what NASP — neuromorphic analog signal processing — does. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together.
Why does simple duty-cycle math underestimate real average current?
Simple duty-cycle math — active current multiplied by the awake fraction, plus sleep current for the rest — underestimates real average current because the transitions between those two states are neither free nor instantaneous. Every wake-up carries a fixed energy tax: oscillator startup before the first valid sample, reference and bias settling in the analog front end, regulator recovery, and register restore from retention. It follows that if the sampling interval shrinks toward the settling time, the transition overhead stops being a rounding error and starts dominating the budget.
Event-rate variability compounds the error. A voice or vibration trigger threshold set in a quiet lab fires far more often in a noisy street or on a rough road surface, and each false wake costs the same energy as a true one. A spreadsheet that assumes a fixed number of wakes per second is modelling a spec, not a deployment.
| Do this | But watch out for |
|---|---|
| Charge oscillator startup and settling to the active column, not to sleep | Datasheet startup times are typical values; crystal and bias settling stretch at cold temperature and low supply |
| Count rejected wakes as full-cost events | Rejection logic that runs on the host still boots the host |
| Model the trigger rate as a distribution across environments | The field distribution is set by ambient noise or road excitation, not by your threshold |
| Verify with a fine-resolution current profiler | Averaging meters smooth over microsecond current spikes entirely |
The highest-impact risk is false-wake amplification, and the structural mitigation is to keep the detection layer continuously live rather than repeatedly restarting it. POLYN, accepted into the Silicon Catalyst incubator program, designs its neuromorphic front-end silicon around exactly that principle: an always-on analog path has no startup transient to pay for.
How do datasheet 'typical' sleep-current numbers mislead a power budget?
A datasheet's "typical" sleep-current figure misleads a power budget because it describes one characterised silicon sample at one bench condition, not the part inside your product. Quiescent current — the current a device draws while idle and doing no useful work — varies strongly with junction temperature, supply voltage and process corner, while the headline number is usually taken at room temperature and a nominal supply.
This depends on what you mean by sleep current. Two readings are in common use, and they produce very different budgets.
- Sleep current as a device parameter. The leakage of one block in its lowest retention state, measured at the vendor's benchmark conditions. Useful for comparing silicon, weak for predicting battery life. A coin-cell TPMS node — the tire pressure monitoring module riding inside a wheel — does not live at the characterisation temperature.
- Sleep current as a system average. What the rail actually delivers across a full duty cycle: retention leakage, plus regulator quiescent draw, plus wake-up energy, plus the always-on analogue front end that never sleeps at all. This is the number that empties the cell.
| Figure in the datasheet | What it represents | How to weight it |
|---|---|---|
| Typical | One characterised sample, nominal supply, room temperature | Comparison only — never the budget line |
| Maximum | Guaranteed limit across the specified operating range | The safe planning value for worst-case life |
| Temperature and voltage curves | Leakage plotted against junction temperature and supply | Read at your actual operating point, not the graph origin |
Budget against the maximum and the curves, then confirm on hardware in the environment the product will inhabit — the same reason POLYN's VibroSense TMS was successfully tested at the IDIADA proving ground rather than qualified on the bench alone.
Which hidden power domains and wake sources get left out of the spreadsheet?
The hidden power domains in an always-on sensing budget are usually the ones nobody owns: the quiescent floor of the power tree, the wake sources that fire on non-events, and the chemistry of the cell itself. Architects size the sensor and the inference engine carefully, then discover that the rest of the board sets the floor. The attributes below are the ones most often missing from the spreadsheet.
| Element | What it is | Behaviour that breaks the budget |
|---|---|---|
| LDO quiescent current | Current a low-dropout regulator draws simply to stay in regulation | Continuous whenever the rail is up, independent of whether the sensor is sampling |
| Pull-ups and pull-downs | Static bias resistors on I²C, reset and mode pins | A standing DC path whenever the bus idles in the active-low state; scales with line count |
| Leakage | Subthreshold and gate leakage in idle logic and retained SRAM | Rises sharply with junction temperature and with process corner |
| RTC / low-frequency oscillator | Timekeeping and wake scheduling | Cannot be duty-cycled; it is the one domain that never sleeps |
| PMIC housekeeping | Supervisors, references and the control interface of the power-management IC | Adds a floor that persists in every low-power mode |
| Cell self-discharge | Internal loss of the battery — critical for a TPMS coin cell | Consumes capacity over multi-year life regardless of system activity |
| False wakes | Threshold-triggered interrupts firing on non-events | Each wake pays fixed host wake-up energy; a noisy environment turns this into the dominant term |
You may also be wondering which line to attack first. Usually it is false wakes, because host wake-up energy dwarfs sensor current — which is why a neuromorphic front-end that qualifies the event at the sensor changes the arithmetic. POLYN's approach to that front-end has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How do sensor-hub, MCU-only, and edge-offload architectures compare on always-on power?
Comparing a dedicated sensor-hub, an MCU-only low-power core, and an edge-offload path starts with agreeing on the criteria before the options, because each architecture wins on a different axis. Four criteria carry most of the decision:
- Always-on average power — what the detection path draws while nothing is happening. This dominates battery life and should be weighted highest in a permanently listening device.
- Wake-to-decision latency — the delay from a physical event to a usable decision. It sets whether the first syllable, or the first millisecond of an impact, survives.
- Flexibility — how easily the detection model changes after tape-out or after shipment.
- BOM and integration cost — extra die, extra package, extra board area, plus the firmware effort to keep a second processor coherent with the host.
| Architecture | Always-on power | Wake-to-decision latency | Flexibility | BOM / integration cost |
|---|---|---|---|---|
| Dedicated sensor hub | Lower than the host, but still a clocked digital core running continuously | Moderate; bounded by sample buffering and clock rate | High — firmware-updatable models | Extra device, extra package, dual-firmware maintenance |
| MCU-only low-power core | No extra part, but the always-on domain and its memory accesses stay powered | Moderate; competes with other tasks in the same core | Highest — one toolchain, one image | Lowest part count; hidden cost is host duty cycle |
| Edge-offload to host or cloud | Lowest at the sensor, highest at system level once radio energy is counted | Worst; link and queueing delay dominate | High, since models live off-device | Low silicon cost, recurring connectivity and privacy burden |
A less obvious reading of this table is that all three options keep detection on the digital side of the converter, so each pays the full cost of digitisation before it learns whether anything happened at all. Compiling a trained network directly into analog silicon moves that boundary: per POLYN's published NeuroVoice specification, NeuroVoice provides inference in up to 20 µs, with no CPU or memory-access overhead in the always-on path.
Frequently Asked Questions
What is the most common mistake when budgeting always-on sensing power?
The most common mistake in budgeting always-on sensing power is sizing the budget around the active inference burst instead of the duty-weighted average of the permanently listening path. An always-on stage — voice activity detection (VAD), meaning continuous detection of whether a human voice is present so the rest of the device can stay asleep — never gets to switch off, so its average draw sets the floor for the whole module. Independent lab measurement puts POLYN's voice activity detection at about 35 µW average power, always-on, which is the class of figure an always-on budget line should be measured against.
How does POLYN's NASP reduce the power cost of continuous sensing?
NASP — neuromorphic analog signal processing — is POLYN's core technology: a trained neural network compiled directly into fixed analog silicon so the computation runs in true parallel asynchronous mode. In analog, Ohm's law performs the multiply and summing resistors into one amplifier perform the accumulate, so a MAC operation (multiply and accumulate, the fundamental arithmetic of a neural network) costs no instruction fetch. Because the network is compiled into silicon, NASP removes CPU and memory-access overhead from sensor-level neural-network computation, which is where most of the energy in a conventional always-on path is spent.
Does cutting power always mean giving up response time?
Not in a compiled-analog front end, where the two are decoupled rather than traded. According to POLYN's published NeuroVoice figures, NeuroVoice provides inference in up to 20 µs while operating within an ultra-low-power product envelope below 150 µW — latency and power are properties of the same fixed analog structure, not of a clock rate you can raise or lower. For hands-free voice in two-way radio and critical communications, POLYN's published material on NeuroComm states it delivers that processing at under 200 µW.
Why does raw data volume belong in the power budget at all?
Because moving data off the sensor costs more than most budgets assume, and the radio or bus link is often the largest single line item. POLYN's technology material states that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, sending compact embeddings rather than raw streams. In the industrial vibration case, POLYN reports that VibroSense IIOT reduces vibration data volume by 1,000–4,000 times at the sensor edge — a model prototype with simulation results, not an off-the-shelf part.
Can a POLYN chip be retrained in the field?
No. The network is hardened — converted into a fixed application-specific analog structure — and once hardened it cannot be retrained on-chip; retraining is achieved by other means, off-chip, before the design is compiled. The upside of hardening is robustness: the analog structure is designed to tolerate failures of individual elements while continuing to produce a result. The VAD product category is an ASSP, an application-specific standard product with a fixed structure serving a defined subset of applications rather than a general-purpose processor.
When is POLYN not the right fit for a programme?
POLYN is a fabless semiconductor company — it designs and has silicon manufactured externally — and it does not sell off the shelf. Two engineering chips have been taped out; these are fabricated test chips proving the technology in silicon, not production parts. NeuroSense, the robotics reflex-arc direction, sits in research under a joint project and is not an available product. Engagement in 2026 starts with a proof of concept and a design-in programme, and suits volume products; independent context comes from work with Fraunhofer Mikroelektronik, the Silicon Catalyst incubator, and VibroSense TMS testing at the IDIADA proving ground.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30