How to Verify a 35 µW Voice Activity Detection Claim

Q: Can the chip be retrained in the field?

No. POLYN's approach uses hardening : the trained network is converted into a fixed, application-specific analog structure in silicon, and once hardened it cannot be retrained on-chip. Retraining is achieved by other means, off the part. A useful property of the analog structure is that it is designed to tolerate failures of individual elements while still producing a result, which is worth probing during evaluation.

At a glance

Verifying a 35 µW voice activity detection claim starts with three questions: measured or simulated, average or peak, and what the always-on path includes.
POLYN Technology states its NeuroVoice voice activity detection runs always-on at about 35 µW average power.
Bench measurement on fabricated silicon and simulation-derived power estimates answer different questions; treat them as separate evidence classes.
POLYN has taped out two engineering chips — fabricated test silicon, not production parts — so NASP claims rest on measurable hardware.
Ask for the measurement conditions in writing before a design-in window, not after evaluation silicon arrives.

POLYN

Published: 2026-08-30

To verify a 35 µW voice activity detection claim, ask three questions before you look at anything else: was the figure measured on fabricated silicon or produced by simulation, is it an average or a peak, and exactly which blocks of the always-on path are inside the measurement boundary. Voice activity detection (VAD) — the always-on function that decides whether a human voice is present so the rest of the device can stay asleep — is trivially easy to quote favourably, because a number that excludes the microphone bias, the analog front end, the clock source or the wake-up interface is not the number your power budget will see. POLYN Technology states that its NeuroVoice voice activity detection runs always-on at about 35 µW average power, and that class of claim is verifiable only when the supplier will state the silicon status, the signal conditions, the input activity assumption and the boundary of the measured block.

That distinction matters more in 2026 than it did when always-on voice detection was a duty-cycled convenience feature rather than a permanent load. POLYN is a fabless semiconductor company — it designs chips and has them manufactured at an external foundry — building neuromorphic analog signal processing (NASP), an architecture in which a trained neural network is compiled directly into analog silicon so the computation runs in parallel with no CPU cycles and no memory accesses. POLYN has taped out two engineering chips: fabricated test devices that prove the technology in silicon, not production parts. For a principal architect judging whether a microwatt figure survives contact with a real module, the rest of this article separates the two evidence classes you will actually be handed — independent bench measurement of fabricated silicon versus simulation-derived power estimates — and sets out what each one can and cannot prove.

What exactly does a 35 µW voice activity detection claim mean?

A stated 35 µW voice activity detection figure means exactly nothing until the measurement boundary is defined — so this section restricts itself to that boundary. Voice activity detection is the always-on function that decides whether human speech is present so the rest of the device can stay asleep, and its power draw depends entirely on which blocks are counted inside the number.

To read any such figure as an architect, pin down these attributes:

Blocks inside the boundary. Allowed values range from the neural classifier alone to the full always-on chain: microphone bias, analog front end, feature extraction, classifier, and any wake-word stage. A classifier-only number is not a system number, and only the full chain maps onto a module budget.
Duty cycle. Values run from continuously biased to heavily gated. "Always-on" in the strict sense means the detector is continuously live rather than periodically sampled — no wake timer, no missed speech onsets — which is why the averaging assumption must be stated rather than inferred.
Supply and rails. A figure moves with the analog supply voltage and with whether microphone bias is drawn from the same rail. Ask which rails are summed into the total.
Signal conditions. Silence, speech, and babble noise draw differently. An average is comparable only when the input scenario and averaging window are identified.
Silicon maturity. The category here is an ASSP — an Application Specific Standard Product, a fixed-structure part built for one class of application — while the first manufactured version of POLYN's detector is an engineering chip: fabricated test silicon that proves the technology, not a production part.

POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, which gives that measurement boundary an external design partner rather than a purely internal definition.

Which measurement conditions make or break a 35 µW number?

Two things break a microwatt-class figure more often than anything else in the measurement conditions: what the number averages over, and what the vendor counts as "the VAD" — voice activity detection, the always-on function that decides whether a human voice is present before the rest of the device wakes.

The first reading is average power over a realistic acoustic duty cycle, including long stretches of silence where the detector idles. The second is instantaneous power while the detector is actively classifying. A part can be honest about one and silent about the other; on a mostly-quiet stimulus track the two differ enough that a single microwatt-class claim carries no meaning until you know which it is.

Ask for these conditions in writing before you compare anything:

Supply rail and rail count. A near-threshold core supply and a standard I/O-referenced supply are not comparable, and figures that exclude the I/O domain understate the always-on path.
Process corner and temperature. Typical-typical at room temperature flatters leakage; a hot, slow corner is the number your product actually ships against.
What is inside the boundary. Clock or oscillator generation, bias currents, reference generation and static leakage belong in the total. Core-only figures are a different measurement.
Stimulus SNR and content. Clean speech in a quiet room and speech in babble noise drive different activation rates, and therefore different averages.
Operating point. False-accept and false-reject rates trade directly against power, because every false accept wakes the downstream processor.
Sample rate and bandwidth. Narrowband and wideband front ends are not the same load.

The reading worth using is average power across the complete always-on path, at a stated operating point, on fabricated silicon. POLYN was accepted into the Silicon Catalyst incubator program, an environment where claims are expected to survive that level of scrutiny.

How do you set up a bench test to verify 35 µW yourself?

Setting up a bench test to verify an always-on voice activity detection power figure is straightforward, but the instrumentation must be chosen before the board is powered up. The claim is an average over a realistic mix of speech and silence, so the measurement chain has to resolve currents well below the level claimed without disturbing the supply rail.

Step	Do this	But watch out for
Instrument	Use a source-measure unit — an instrument that sources voltage and measures current simultaneously — or a precision current probe with sub-microamp resolution and auto-ranging	Burden voltage: the drop across the sense shunt sags the rail and changes device behaviour, invalidating the reading
Rail isolation	Break out the neuromorphic front-end chip's supply separately from MEMS microphone bias and host MCU rails	A bundled rail attributes the microphone's and host's current to the chip under test
Dynamic range	Confirm range switching covers idle current and wake-event peaks in one continuous capture	Range-change glitches drop samples exactly where the peaks are, understating the average
Averaging window	Average across a full corpus containing both speech and long silence	Averaging over silence alone reports an idle floor, not average power
Stimulus	Replay a standard audio corpus at calibrated sound pressure level through a coupler, including noisy conditions	Clean studio audio flatters detection accuracy and misrepresents field use
Accuracy logging	Log false-accept and false-reject rates on the same timeline as current	Sensitivity can be quietly traded down to buy power; the two numbers are only meaningful together

The highest-impact risk is burden voltage: mitigate it with a four-wire connection and verify rail voltage at the device pin during capture. It follows that system-level claims deserve the same discipline — VibroSense TMS was successfully tested at the IDIADA proving ground rather than on a bench alone.

How does a 35 µW VAD compare with other low-power detection approaches?

To compare a microwatt-class VAD — voice activity detection, the always-on function that decides whether a human voice is present before waking anything else — with other low-power detection approaches, fix the evaluation criteria before looking at any part. Two architectures are genuinely distinct here: POLYN's NASP (Neuromorphic Analog Signal Processing) front-end, where the detection network exists as fixed analog circuitry rather than as executable code, and the conventional digital path, where a DSP block, an MCU software library, or a microphone-integrated detector runs the same decision as clocked arithmetic.

Which criteria should carry the most weight?

Average power in the always-on state. This is the binding constraint, not peak power. A detector that only meets its budget when duty-cycled is not always-on.
Response latency. Time from acoustic event to wake decision, which sets how much of the first syllable survives.
Accuracy at low SNR. A cheap detector that false-triggers in a noisy cabin transfers its cost to whatever it wakes.
Silicon area and memory footprint. Area competes with the sensor die; memory matters because digital inference spends much of its energy on memory access, not arithmetic.
Integration effort. Design-in cost at module level, including what the host must still do.

Criterion	NASP analog front-end (NeuroVoice)	Conventional digital VAD (DSP / MCU software / mic-integrated)
Always-on power	Microwatt class; no clocked compute	Set by clock rate and memory traffic
Latency	Continuous and asynchronous — decision available as the signal arrives	Frame-buffered; bounded by frame length
Low-SNR behaviour	Network trained on noisy data, hardened into the structure	Depends on model size the budget allows
Memory footprint	No weight fetches — the weights are the circuit	Weights and activations held in RAM
Integration	Front-end block ahead of the host	Firmware plus host processing budget

POLYN's work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session — useful third-party reading when you audit these criteria yourself.

Why do datasheet power figures diverge from in-system measurements?

When a bench reading and a datasheet power figure disagree, the datasheet figures are usually not wrong — the two numbers measure different boundaries. A published power figure for a voice activity detection (VAD) part, meaning always-on detection of whether a human voice is present, describes the die under a stated supply, clock and stimulus. Your system meter sees the MEMS microphone bias, the codec or PDM interface, regulator conversion loss, board leakage across the whole always-on rail, and every downstream block the detector wakes. If you are evaluating a neuromorphic front-end chip — a part that pre-processes sensor data with a neural network before the host sees it — the boundary question decides whether the comparison is fair.

Do this in your evaluation	But watch out for
Measure at the module rail, not the die pin	You now include microphone and codec draw that the component figure never claimed
Include the LDO or buck in the loop	Conversion efficiency collapses at microampere loads, inflating the reading
Count the wake-up cascade, not just the detector	Host boot, clock settling and DMA setup can exceed the detector's own consumption
Log false accepts over a realistic acoustic day	Each false accept pays the full downstream wake cost, so accuracy is a power parameter
Model battery life from measured duty cycle	Averaging a bench number over an assumed duty cycle yields a spreadsheet result, not a device result

The highest-impact risk is the false-accept cascade, because it turns a detection-quality problem into a power problem. Mitigate it by measuring detection accuracy and wake energy together, and by checking how quickly the front end resolves: per POLYN's published NeuroVoice specification, inference runs in up to 20 µs, which bounds how long the wake path stays energised per decision.

What should you ask a vendor before accepting the claim?

Before you accept any microwatt figure, ask the vendor for the measurement conditions in writing — the questions below separate a silicon-measured result from a simulator plot with a favourable input file. Voice activity detection (VAD) means always-on detection of whether a human voice is present, so its power number is only meaningful alongside the acoustic input it was fed and the accuracy it held while doing it.

A due-diligence checklist to send with the NDA

Silicon or simulation? Was the figure measured on fabricated silicon or extracted from a netlist simulation? Ask whether the part measured is an engineering chip — a fabricated test chip that proves the technology but is not a production part.
Sample size and lots. How many dies, from how many wafer lots, and what is the spread across process corners, supply voltage and temperature?
Accuracy operating point. At what false-accept and false-reject rates was the power recorded, on which speech and noise corpus, at what signal-to-noise ratios?
Duty profile. Is it average power over a defined activity profile, or the idle-listening floor only?
Reproducibility. Can you obtain an evaluation board, the test scripts and the bench setup to repeat it yourself?
Independent corroboration. Which third party has seen the bench?

What most datasheet arguments miss is that a VAD power figure is not a scalar at all but a triple — power, error rates, and input activity — and a vendor that will not publish all three has published none of them.

Frequently Asked Questions

These answers address the practical questions engineering teams raise when they set out to verify a 35 µW voice activity detection claim before committing to a design-in evaluation.

What exactly does the 35 µW number measure?

Voice activity detection (VAD) is the always-on function that decides whether a human voice is present, so the rest of the device can stay asleep until someone speaks. POLYN Technology states that its voice activity detection runs always-on at about 35 µW average power. The operative word is average: a credible verification asks what sits inside the measurement boundary, what the acoustic input was during the window, and whether the host processor stayed asleep throughout. A peak-power reading, a figure taken with the microphone bias excluded, or a short capture window are all different quantities and should not be compared directly.

How should an evaluation team measure it on the bench?

Reproduce the measurement rather than accept a single datasheet line. A defensible bench protocol looks like this:

Fix the measurement boundary and state it — which rails, which supporting components, and whether the MEMS microphone bias is inside or outside the number.
Integrate current over a long window with an instrument suited to sub-milliwatt averages, not a spot reading from a bench multimeter.
Drive the device with a repeatable audio corpus that mixes speech, silence and realistic background noise, so the duty cycle is not artificially favourable.
Log detection outcomes alongside power, because a low average power figure achieved through missed speech is not the same result.
Confirm the host stays in its deep-sleep state for the whole run; a wake-up the VAD triggers unnecessarily lands in the system budget, not the chip's.

Why does inference latency belong in the same conversation?

Power and response time are usually traded against each other, so a power figure is only meaningful next to a latency figure. According to POLYN's published NeuroVoice material, the product provides inference in up to 20 µs. That is possible because NASP — neuromorphic analog signal processing, POLYN's technique of compiling a trained neural network directly into analog silicon — removes CPU and memory-access overhead from the sensor-level computation. Verification should therefore capture both axes in one run: average power and time-to-decision under the same stimulus.

Can the chip be retrained in the field?

No. POLYN's approach uses hardening: the trained network is converted into a fixed, application-specific analog structure in silicon, and once hardened it cannot be retrained on-chip. Retraining is achieved by other means, off the part. A useful property of the analog structure is that it is designed to tolerate failures of individual elements while still producing a result, which is worth probing during evaluation.

Is the silicon a production part?

Not yet. POLYN has demonstrated its technology in fabricated silicon rather than in simulation alone — two engineering chips have been taped out. An engineering chip proves the technology in silicon but is not a production part. Separately, the VAD product category itself is an ASSP, an Application Specific Standard Product: a fixed-structure device built for a specific application subset rather than a general-purpose processor. Per POLYN's published NeuroVoice material, the product operates within an ultra-low-power envelope below 150 µW.

What independent evidence exists beyond POLYN's own bench?

Several external reference points can be checked directly. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and POLYN was accepted into the Silicon Catalyst incubator program. The work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.

About this article

POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30