At a glance
- A proof of concept for analog neural silicon validates one narrow inference task against measured power, latency and accuracy targets before design-in.
- Scope the PoC around a single trained network, a fixed sensor interface, and pass/fail thresholds agreed with the silicon partner.
- POLYN's NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead at the sensor.
- Independent validation matters: VibroSense TMS was successfully tested at the IDIADA proving ground.
- Plan for hardening — once compiled into analog structure, the network is fixed; retraining happens off-chip, not on the part.
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A proof of concept for analog neural silicon is a bounded engineering exercise that answers one question: does a trained neural network, compiled into fixed analog circuitry beside the sensor, meet your power, latency and accuracy budget for a single defined task? Planning one means selecting that task, freezing the dataset and the network topology, defining measurable pass/fail thresholds in microwatts and microseconds, and agreeing with the silicon partner on how results will be measured and by whom. Everything else — multi-function flexibility, production packaging, supply commitments — belongs to a later design-in phase, not to the PoC. In 2026, the practical reason architects run this exercise at all is that conventional digital front-ends force a trade between response time and power budget: faster sampling and inference costs energy the always-on path does not have.
Analog neural silicon differs from a digital accelerator in mechanism, and that difference shapes how the PoC must be structured. In neuromorphic analog signal processing (NASP) — POLYN Technology's core technology — the multiply-and-accumulate operation that underpins every neural network is performed by physics rather than arithmetic: Ohm's law provides the multiply, and summing currents into an amplifier provides the accumulate. The trained network is hardened into an application-specific analog structure, so the computation runs in true parallel asynchronous mode with no CPU cycles and no memory access. That also means the network cannot be retrained on the part; retraining is handled off-chip and re-hardened. A well-planned PoC therefore front-loads dataset and model decisions, because those decisions are what get committed to silicon.
What exactly is a proof of concept for analog neural silicon?
A proof of concept for analog neural silicon is exactly one thing: a bounded demonstration that a specific trained network, implemented as analog circuitry next to a sensor, hits a named power, latency and accuracy target on real signal data. It is not a product programme, not a full ASSP (Application Specific Standard Product — a fixed-structure chip serving a defined application subset), and not a general benchmark of "AI at the edge". The scope restriction is the point: one signal, one network, one budget.
Before any design work begins, a planner has to settle six things. Each is a term of art with a concrete consequence for scope and schedule.
| Term or decision | What it means | Why it decides the PoC |
|---|---|---|
| Analog in-memory computing | Computation performed where weights are physically stored, rather than fetched from memory | Removes memory-access energy from the inference path |
| Crossbar array | Grid of programmable conductances forming a weight matrix | Sets achievable network width and layer topology |
| MAC operation | Multiply-and-accumulate: Ohm's law gives the multiply (V = I × R), summed currents into an amplifier give the accumulate | The single clearest reason analog suits neural arithmetic |
| ADC/DAC overhead | Converter resolution and sample rate at the analog-digital boundary | Often dominates the power budget if placed carelessly |
| Tape-out | Release of the finished layout to the foundry | Hard deadline; nothing changes after it |
| MPW shuttle | Multi-project wafer run sharing reticle area across designs | Fixes the calendar and the die-area allocation |
Fabless design teams — companies that design silicon and have an external foundry manufacture it — should also fix the target process design kit early, since analog behaviour does not port cleanly between nodes. Collaborative validation is common practice at this stage: POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, an arrangement that pairs architecture work with independent design and test capability.
Which workloads and network models should the PoC actually target?
This depends on what you mean by a demonstration workload — the network models that suit analog silicon are not the ones that suit a GPU benchmark, and picking the wrong class of workloads sinks a proof of concept before tape-out. Two readings of "demonstration" are common, and they lead to different scopes.
Reading one: accuracy parity. Here the goal is to show that the analog implementation matches a digital baseline on a standard task — keyword spotting, for example, where a small classifier decides whether one of a few command words was uttered. This is a legitimate scope, but it exercises only the arithmetic. It says nothing about whether the part fits an always-on budget.
Reading two: envelope proof. Here the goal is to show a specific function running inside a stated microwatt and microsecond envelope next to the sensor — voice activity detection ahead of a MEMS microphone, or vibration-signature reduction ahead of a wireless link. This is the reading that matters to an architect who owns the power budget, and it is the one to choose.
Once the scope is fixed, match the model to what an analog crossbar can credibly hold. In neuromorphic analog signal processing, the multiply-and-accumulate — the core arithmetic of any neural layer — is performed by Ohm's law and summed currents, so the practical constraints are these:
- Model size: compact feed-forward and 1-D convolutional front ends, not large attention stacks whose weight matrices are computed at runtime.
- Weight precision: moderate precision, since analog weights are physical elements rather than stored words.
- Sparsity: pruned topologies directly reduce die area.
- Stability: the network must be final before hardening, because a hardened analog structure is fixed and retraining happens off-chip.
POLYN specifies its own NASP products in exactly these envelope-first terms: a stated average power figure bound to a stated inference latency for one defined function, rather than a general benchmark score.
How do you set accuracy, TOPS/W, and area success criteria before tape-out?
Set the exit criteria before tape-out, not after silicon returns: accuracy, energy efficiency expressed as TOPS/W (tera-operations per second per watt), and die area are the three axes on which an analog neural proof of concept is judged. Define and weight each one first; only then compare candidate network topologies against them.
Because the trained network is hardened — converted into a fixed application-specific analog structure that cannot be retrained on-chip — it follows that every criterion must be measured on the compiled network under process, voltage and temperature variation, not on the floating-point model in TensorFlow or PyTorch. A baseline that lives only in a training framework will flatter the design.
| Criterion | What to measure | Why it matters | Weighting guidance |
|---|---|---|---|
| Accuracy delta | Top-1 or task-specific score of the compiled analog network versus the digital reference | The only figure the application owner recognises | Gate first: if the delta is unacceptable, no efficiency number rescues it |
| Energy per inference | Joules per event, averaged over the real duty cycle | Always-on budgets are set in average power, not peak | Highest weight in battery-bound modules |
| Effective TOPS/W | Efficiency including ADC/DAC and bias overhead, not the core array alone | Converters often dominate the analog front-end budget | Reject any figure quoted core-only |
| Silicon area | Post-layout area in the target foundry PDK | Determines whether the block fits inside the sensor module | Weight against integration constraints |
| Yield threshold | Share of parts meeting the accuracy gate across corners | Analog spread decides manufacturability | Set with the foundry before layout |
System-level gates belong on the same list. VibroSense TMS was successfully tested at the IDIADA proving ground — an exit criterion expressed in vehicle behaviour rather than bench conditions, which is how automotive programmes ultimately validate a sensor-edge part.
How does analog compute compare with digital NPUs and FPGA baselines in a PoC?
Before you compare analog compute against digital baselines, fix the evaluation criteria — a proof of concept that scores every axis equally will pick the wrong part. Weight them in this order:
- Energy per inference — the binding constraint in any always-on path. Weight it highest when the feature dies if the power budget is exceeded.
- Precision and determinism — digital arithmetic is bit-exact and repeatable; analog multiply-accumulate (MAC — the multiply-and-add that is the core arithmetic of a neural network, realised in analog through Ohm's law and summing nodes) is statistical, so the PoC must measure task-level accuracy, not bit-level error.
- Programmability after fabrication — can the network change once silicon exists?
- Maturity — is there fabricated silicon, or only simulation?
- PoC cost and schedule — non-recurring engineering plus the time to a measurable result.
| Criterion | Analog neuromorphic front-end | Digital NPU / ASIC block | FPGA emulation |
|---|---|---|---|
| Energy per inference | Lowest; no clocked datapath, no memory fetch | Moderate; dominated by SRAM access and clocking | Highest; fabric overhead makes it unrepresentative |
| Precision | Statistical, validated at task level | Bit-exact, deterministic | Bit-exact, matches target ASIC |
| Programmability | Fixed once hardened; the network is updated off-chip and re-emitted | Firmware-updatable within the fixed datapath | Fully reconfigurable |
| Maturity | Fabricated engineering chips exist | Widely deployed in SoCs | Mature as a development vehicle only |
| PoC cost | Mask and characterisation cost; strongest signal | Moderate; IP licence plus integration | Lowest cash cost, weakest power evidence |
FPGA emulation answers whether the network works; it cannot answer whether it fits the microwatt budget, because the fabric's own overhead swamps the measurement. That distinction is why silicon evidence matters, and why POLYN's neuromorphic analog signal processing work has been examined publicly — covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
Verdict: use FPGA for functional sign-off, a digital block where the network must stay field-updatable, and analog silicon where the power envelope is the requirement.
Which silicon route fits a first test chip: MPW shuttle, full mask set, or emulation?
When choosing which silicon route fits a first test chip, the decision is rarely between MPW shuttle, full mask set, and emulation as equals — for a proof of concept the multi-project wafer (MPW) shuttle almost always fits, because it shares one reticle and one mask set across several designs and removes the dominant non-recurring cost of a dedicated tape-out. A full mask set suits a design already frozen for volume; emulation is a stage, not a destination.
If you are at the consideration stage — technology plausible, budget not yet committed — the sequence below is the one to plan against:
- Behavioral model. Train and validate the network in a standard framework such as TensorFlow or PyTorch, then quantify accuracy loss under analog non-idealities: offset, noise, component tolerance, temperature drift.
- SPICE and Verilog-A co-simulation. Replace the behavioral layers with transistor-level and analog-behavioral blocks against the target foundry PDK. This is where a compiled analog network's latency claim is either confirmed or falls apart.
- FPGA-in-the-loop emulation. Stream real captured sensor data — microphone, accelerometer, tire vibration — through the digital wrapper and the modelled analog core to check system-level behavior before committing to a shuttle slot.
- MPW shuttle test chip. Book against the shuttle calendar; slots are scheduled rather than available on demand, so the schedule risk sits in queueing, not fabrication.
- Characterization board. Measure power, latency and detection quality on real silicon, in the enclosure and the acoustic or mechanical environment the product will actually see.
The recurring failure mode in analog proof-of-concept work is one of scoping rather than physics: the experiment gets built to settle accuracy when the load-bearing question was latency and power. POLYN's NeuroVoice, per its product documentation, provides inference in up to 20 µs — a figure that only carries weight once a characterization board has reproduced it outside simulation.
Frequently Asked Questions
What is a proof of concept for analog neural silicon?
A proof of concept for analog neural silicon is a bounded technical evaluation that tests whether a trained neural network, compiled directly into fixed analog circuitry, meets a product's power, latency and accuracy budgets before any design-in commitment. The evaluation targets neuromorphic analog signal processing (NASP) — POLYN's approach, in which the network becomes a physical arrangement of resistors and amplifiers rather than software running on a processor. A well-scoped proof of concept answers one question per budget line: microwatts, microseconds, die area, and detection quality against the customer's own recorded sensor data.
Which success metrics should the evaluation define up front?
Define the acceptance thresholds before silicon or model work begins, because an analog front-end is judged on the budgets it displaces, not on benchmark scores. Four metrics usually carry the decision:
| Metric | Why it decides the design-in |
|---|---|
| Average always-on power | POLYN Technology states its NeuroVoice voice activity detection — always-on detection of whether a human voice is present — runs at about 35 µW average power. |
| Inference latency | POLYN's published NeuroVoice material specifies inference in up to 20 µs, which sets whether a reflex-speed response is possible at all. |
| Data reduction at the edge | POLYN's technology documentation states NASP can cut raw sensor-data flow by approximately 1,000× through on-sensor neural processing. |
| Detection quality | Measured on the customer's own captured data, not on a public dataset. |
What data and tooling does the customer need to supply?
The customer supplies labelled sensor recordings from the target environment — microphone captures, accelerometer traces from inside a tire, or vibration records from a machine — plus the acceptance thresholds the feature must clear. Network training uses standard frameworks such as TensorFlow, PyTorch or MXNet; POLYN also has a partnership with Edge Impulse to advance Tiny AI products. POLYN then hardens the trained network: converting it into a fixed application-specific analog structure so the computation runs in parallel with no CPU cycles and no memory accesses.
Can the chip be retrained after it is hardened?
No. Once a network is hardened into analog silicon, that structure is fixed and cannot be retrained on-chip; retraining is achieved by other means, outside the part. This is a deliberate architectural trade, and it should be planned for in the proof of concept: the evaluation must confirm that the trained network generalises across the conditions the product will actually meet, since the deployed structure will not adapt in the field. The upside is that removing the processor and memory hierarchy is what makes the microwatt envelope achievable — POLYN's published NeuroVoice figures place the product within an ultra-low-power envelope below 150 µW.
How mature is the silicon a proof of concept can build on?
POLYN has demonstrated its technology in fabricated silicon rather than simulation alone: two engineering chips have been taped out. An engineering chip is a fabricated test device that proves the technology in silicon but is not a production part, and the distinction matters when a program manager assesses schedule risk. Separately, the voice activity detection product category is an ASSP — an Application Specific Standard Product, a fixed-structure chip serving a defined subset of applications rather than a general-purpose processor. The two terms answer different questions: one describes the product class, the other the current silicon's maturity.
How can the claims be verified independently?
Several reference points sit outside POLYN. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and POLYN was accepted into the Silicon Catalyst incubator program. On the automotive side, VibroSense TMS — which reports peak friction coefficient, the grip available at the tire-road contact, across the 0–1 range in 0.1 steps per POLYN's product documentation — was successfully tested at the IDIADA proving ground. The work has also been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30