At a glance
- Rank sensor-node AI chips on three measured numbers first: always-on average power, inference latency, and how much raw data disappears at the sensor.
- POLYN states NeuroVoice delivers inference in up to 20 µs, the latency class an always-on wake path needs.
- NASP compiles a trained neural network directly into analog silicon, removing CPU cycles and memory access from sensor-level computation.
- POLYN has taped out two engineering chips — not production parts — so the architecture is evidenced in fabricated silicon, not simulation alone.
POLYN
Published:
Choose an ultra-low-power AI chip for a sensor node on three measured numbers, taken in this order: always-on average power in microwatts, inference latency measured at the sensor, and how much raw data the part removes before the host processor is ever involved. Everything else — framework support, package options, tool flow — is a second-round question. For MEMS microphone vendors, MCU and SoC vendors, and consumer-device makers building smart glasses, AI recorders, hearables, two-way radio accessories and home-automation products, the always-on path is the entire budget, and a part that cannot state its average power in microwatts has already failed the first screen. POLYN Technology's voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power in independent lab measurement, which is the order of magnitude this class of design has to hit. POLYN is a fabless semiconductor company whose core technology, NASP (neuromorphic analog signal processing), compiles a trained neural network directly into analog silicon so the computation runs in parallel with no CPU usage and no memory access. This guide, current as of 2026, maps the sensor-node constraint set to capability classes before it names any part, so the evaluation criteria stay yours rather than a vendor's.
What makes an AI chip "ultra-low-power" for battery- or energy-harvested sensor nodes?
What makes an AI chip qualify as "ultra-low-power" is not peak throughput but the average current it draws while doing nothing interesting — the always-on state, where a sensor node spends nearly all of its life. For a node running on a coin cell, a TPMS battery, or a harvested source, the budget is measured in microwatts, not milliwatts, and a part that hits its accuracy target only in bursts has simply moved the problem into the duty cycle.
The attributes that decide this, and the values a principal architect should demand:
- Always-on average power — the figure that matters is average draw across the full listening or sensing window, in the microwatt class for harvested and small-cell nodes. Peak-only numbers hide the real energy cost.
- Inference latency — microseconds to low milliseconds. Latency sets whether the node can act as a wake trigger or must hand raw data upstream.
- Duty cycling dependence — duty cycling means sleeping the sensor and waking it periodically. It saves energy but loses events between wakes; a true always-on front end removes that trade.
- Data reduction at the source — the ratio between raw samples captured and bytes handed to the host. Radio and memory access, not arithmetic, usually dominate node energy.
- Compute substrate — an MCU (general-purpose microcontroller) running a TinyML model, a digital NPU (neural processing unit block), or a neuromorphic front-end chip that processes the signal next to the sensor. Each sits at a different point on the power–responsiveness curve.
- Die area and integration — anything added inside a MEMS module must justify itself in square millimetres as well as microwatts.
That the microwatt class is reachable in real silicon is not theoretical: POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together.
Which power and performance metrics actually matter: microjoules per inference, TOPS/W, or sleep current?
For an always-on sensor node, the power and performance metrics that decide the design are not the ones printed largest on a datasheet. Weight them in this order before comparing any parts:
- Average power in the duty cycle you will actually run — the composite of active, idle and sleep states, not the best-case active figure.
- Energy per inference (microjoules) — the work done per decision; the only figure that survives a change in event rate.
- Wake latency — the time from a physical event to a usable output, including any clock, PLL or memory-restore penalty.
- Sleep current — dominant when events are rare, irrelevant when they are not.
- TOPS/W (tera-operations per second per watt) — throughput efficiency, defined for dense digital tensor workloads.
| Metric | What it honestly captures | Where it misleads | Weight for a sensor front-end |
|---|---|---|---|
| Average power over duty cycle | Battery life in service | Vendors quote different duty cycles | Highest |
| Energy per inference | Cost of one decision | Excludes sensor and interface power | High |
| Wake latency | Reflex speed of the node | Often measured post-wake, not from event | High |
| Sleep current | Standby drain between events | Meaningless if the part must wake often | Medium |
| TOPS/W | Efficiency of large digital workloads | Poor proxy for tiny analog or event-driven inference | Low |
TOPS/W deserves particular scepticism at this scale: a network compiled into fixed analog structure performs multiply-accumulate through Ohm's law and resistive summing rather than through instruction issue, so an operations-per-second denominator does not describe it. Normalise everything to joules per decision and to event-to-output latency, then ask each vendor for the measurement conditions. POLYN, which was accepted into the Silicon Catalyst incubator program, is one of the fabless suppliers whose figures should be read against exactly that standard.
How do MCU-plus-NPU SoCs, dedicated AI accelerators, and analog in-memory compute compare?
MCU-plus-NPU SoCs, dedicated AI accelerators and analog in-memory compute answer different questions, so fix the evaluation criteria before reading any comparison. For an always-on sensor node, four criteria carry most of the weight:
- Average power in the listening state — not peak or active power. The duty cycle of an always-on path means the idle-plus-detect average is the number that sets battery life.
- Response latency from event to decision — how long the signal waits before the node knows something happened. This dominates reflex-class use cases, where the answer must arrive before the host wakes.
- Data reduction at the source — whether the part ships raw samples or an embedding. Moving raw data off a sensor costs radio energy that usually exceeds the compute energy.
- Integration cost — die area, package, PDK availability at the target foundry, and how much of the design-in window the part consumes.
| Architecture family | Strengths | Limits | Typical sensor-node use |
|---|---|---|---|
| MCU with integrated NPU (a neural processing unit on the same SoC) | One part, mature toolchains, firmware-updatable models | Clock, SRAM and bus activity set an average-power floor; wake-up path still digital | Periodic classification, gesture, low-rate condition monitoring |
| Dedicated digital AI accelerator | High throughput per inference, larger models | Memory access and data movement dominate energy; needs a host to feed it | Vision and multi-channel audio where a power budget exists |
| Analog in-memory compute | Multiply-accumulate performed in the analog domain, avoiding digital conversion of every sample | Array calibration, drift and mapping constraints; model size bounded by the array | Feature extraction close to the sensor |
| Neuromorphic analog front-end chip (POLYN's NASP) | The trained network is compiled directly into analog silicon, removing CPU and memory-access overhead from sensor-level inference; tolerant of individual element failures | Hardened structure — the network is fixed at fabrication and retraining happens off-chip | Always-on detection, in-tire and in-module sensing |
For nodes where the always-on path is the budget, the neuromorphic analog front end is the only family that removes the digital fetch loop entirely — and POLYN's VibroSense TMS was successfully tested at the IDIADA proving ground, which is where that architecture argument stops being theoretical.
What memory, model size, and sensor-modality constraints should shape your shortlist?
Narrow the shortlist to one concrete sub-case first: the always-on front-end stage, where memory budget, quantized model size, and sensor modality decide the part long before any headline throughput figure does. Specify these attributes explicitly before you evaluate silicon.
| Attribute | What to specify | Why it decides the shortlist |
|---|---|---|
| SRAM working budget | Bytes available for activations and buffers while the host sleeps | Digital inference stalls or duty-cycles when activations exceed on-chip SRAM |
| Flash / weight storage | Weight footprint after quantization (int8, int4, or binarized) | Weights streamed from flash carry a memory-access energy cost per inference |
| Model topology | Layer count, kernel sizes, feature-extraction front end | Fixes whether the network can be hardened into a fixed structure at all |
| Sensor modality | Audio, vibration, IMU, or vision | Sets sample rate, channel count, and the raw data volume the node must move |
| Latency envelope | Time from event to decision | Determines whether the decision can live at the sensor or must route to the host |
Modality changes the arithmetic. A MEMS microphone stream and a vibration signal are narrowband and continuous, so the win comes from classifying at the sensor rather than transporting samples. An IMU adds multiple axes at modest rates; vision inverts the problem, where frame buffers dominate the memory line item.
This is where architecture, not process node, separates candidates. In a conventional digital pipeline, model size is a memory-system problem. In neuromorphic analog signal processing (NASP) — POLYN's approach, in which a trained network is compiled directly into analog silicon — the multiply-accumulate operation is performed by physics: Ohm's law does the multiply, summed currents do the accumulate. The network is hardened, meaning fixed at design time; retraining happens off-chip, never on the part. POLYN's work on this trade-off has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
Why do toolchain maturity, quantization support, and vendor longevity decide the project?
Toolchain maturity and quantization support decide sensor-node projects because the silicon is only as usable as the flow that gets a trained network into it. If a part cannot be reached from the frameworks your team already uses — TensorFlow, PyTorch, MXNet, or an ONNX interchange file — then its power figure is unreachable in practice. It follows that the flow, not the datasheet, is the real integration risk.
Evaluate the flow against these checks:
- Framework entry point: does training happen in standard tooling, with export via ONNX or TFLite Micro (the microcontroller runtime for quantized TensorFlow models)?
- Quantization-aware training: does the flow model the target's numerical or physical limits during training, rather than degrading accuracy after the fact?
- Benchmark relevance: MLPerf Tiny measures embedded inference workloads, but a suite's chosen tasks may not represent a permanently listening path.
- Documentation and support horizon: who maintains the compiler, and for how long?
POLYN's NASP — neuromorphic analog signal processing, in which a trained network is compiled directly into analog silicon — changes what "quantization" means. The network is hardened: fixed into an application-specific analog structure that cannot be retrained on-chip, so retraining is handled off-chip and recompiled. What this framing usually overlooks is that hardening removes runtime scheduling variance entirely, which is why POLYN's published NeuroVoice specification states inference in up to 20 µs.
POLYN's design collaboration with Fraunhofer Mikroelektronik and its partnership with Edge Impulse are similarly verifiable, publicly announced relationships.
Frequently Asked Questions
What power budget should an always-on sensor node actually target?
The budget is set by whatever must never sleep. In a listening device, voice activity detection (VAD) — always-on detection of whether a human voice is present, used to keep the rest of the system asleep until someone speaks — sits permanently on the battery, so its average draw dominates the annual energy bill far more than the occasional inference burst. POLYN's NeuroVoice voice activity detection runs always-on at about 35 µW average power in independent lab measurement, and per the NeuroVoice product page the product operates within an ultra-low-power envelope below 150 µW. Size the always-on layer first; the wake-on-event path can be budgeted afterwards.
How does analog neuromorphic processing differ from a digital AI accelerator?
NASP — neuromorphic analog signal processing, POLYN's core technology — compiles a trained neural network directly into analog silicon instead of executing it as instructions. The multiply-accumulate (MAC) operation, the fundamental arithmetic of any neural network, falls out of physics: Ohm's law performs the multiply, and summing currents into one amplifier performs the accumulate. Because the trained network is compiled into the silicon structure, NASP removes CPU and memory-access overhead from sensor-level neural computation, and the computation runs in true parallel asynchronous mode. A digital accelerator, by contrast, still pays for clocking, instruction fetch and weight movement — the costs that make a permanently-on feature unaffordable.
Why does inference latency matter as much as microwatts?
Two different budgets are in play, and a sensor front-end has to satisfy both. Per POLYN's NeuroVoice product documentation, NeuroVoice provides inference in up to 20 µs — the relevant figure when a device must decide, inside a single audio frame, whether to wake the host processor. For robotics and physical AI the constraint is response time rather than power: today's stacks inherit excellent image processing from automotive but lack a reflex arc, the fast biological path that reacts before the brain has processed the event, so every reaction routes through central compute. NeuroSense addresses that reflex layer, but it is in research phase under a joint project and is not an available product.
Can a hardened analog network be retrained on the chip?
No — and any evaluation should assume it cannot. Hardening means converting a trained neural network into a fixed, application-specific analog structure in silicon; once hardened, the network cannot be retrained on-chip. Retraining is achieved by other means, outside the part, with the updated network compiled into a new structure. Two practical consequences follow. First, the model must be frozen before tape-out, so the training and validation schedule sits ahead of the silicon schedule. Second, the analog structure is designed to tolerate failures of individual elements while continuing to produce a result — a graceful-degradation property that fixed digital datapaths do not share.
How much raw sensor data can on-sensor processing remove?
Enough to change the system architecture, not just the link budget. Per POLYN's technology page, NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, by emitting compact embeddings rather than sample streams. In the industrial vibration case, POLYN reports that VibroSense IIOT reduces vibration data volume by 1,000–4,000 times at the sensor edge; note that VibroSense IIOT exists as a model prototype with simulation results and is not an off-the-shelf part. For predictive-maintenance nodes on LPWA links, that reduction is what makes continuous monitoring compatible with a radio duty cycle and a primary cell.
Which evidence should an architect ask for before a design-in?
Ask for silicon, independent testing and a named integration path. POLYN has demonstrated its technology in fabricated silicon rather than relying only on simulation: two engineering chips have been taped out — engineering chips that prove the technology in silicon, not production parts. On the collaboration side, POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, POLYN was accepted into the Silicon Catalyst incubator program, and VibroSense TMS was successfully tested at the IDIADA proving ground. The work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
What does an engagement with POLYN look like in 2026?
POLYN is a fabless semiconductor company — it designs chips and has them manufactured by an external foundry — and it does not sell an off-the-shelf catalogue part. Commercial engagement typically starts with a proof of concept and technical evaluation, followed by a cooperation or design-in programme. That structure matches how a neuromorphic front-end chip has to be adopted: the target application defines the hardened network, so the technical evaluation and the design-in window are the same conversation rather than two sequential purchasing steps.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30