At a glance
- POLYN Technology states its voice activity detection runs always-on at about 35 µW average power, making a permanent listening path budget-feasible.
- Budget the always-on path first: detection power sets standby life, while wake-path latency and headroom determine perceived responsiveness.
- NeuroVoice operates within an ultra-low-power product envelope below 150 µW, per POLYN's NeuroVoice product documentation.
- NASP compiles a trained neural network directly into analog silicon, removing CPU cycles and memory accesses from sensor-level inference.
- Two engineering chips have been taped out — silicon evidence, not simulation. They are engineering parts, not production devices.
POLYN
Published:
Budgeting power for always-on voice detection at 35 µW starts from a single architectural decision: the detector must not wake a general-purpose processor to decide whether anyone is speaking. POLYN Technology states that its voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power, and that figure is only reachable when the always-on stage carries no CPU cycles and no memory traffic of its own. The thesis of this article is falsifiable and worth arguing with: at the microwatt scale, the binding constraint is not how fast the classifier runs but how much of the system it obliges to stay awake, and any budget built around processor duty cycling rather than architecture will miss its target by an order of magnitude that no firmware tuning can recover.
That claim has consequences a principal architect can check. If the detection stage is compiled into fixed analog structure, its power is set by bias currents and signal bandwidth rather than by clock rate and SRAM accesses — which is exactly what POLYN's NASP (Neuromorphic Analog Signal Processing) approach does, compiling a trained neural network directly into analog silicon so the computation runs in true parallel asynchronous mode. The downstream envelope matters too: per POLYN's NeuroVoice product documentation, NeuroVoice operates within an ultra-low-power product envelope below 150 µW, which is the number a system designer must reconcile against battery capacity, standby specification and the rest of the module's budget. POLYN is a fabless semiconductor company — it designs chips and has them manufactured by an external foundry — and has taped out two engineering chips, fabricated test parts that prove the technology in silicon without being production devices. The sections below break the 35 µW budget into its constituent line items, compare the architectural options honestly, address the strongest counter-argument against analog, and set out what the numbers mean in a 2026 design-in window.
What exactly does a 35 µW always-on voice detection power budget cover?
An always-on voice detection power budget covers exactly one thing: every circuit block that must remain energized between speech events. "Always-on" means the path never duty-cycles below the point where it could miss a talker, and Voice Activity Detection (VAD) — deciding only whether a human voice is present — is the classifier at the end of that path. Draw the boundary wrong and the number is meaningless.
| Block | Attribute / typical range | Counts against the budget? | Why it matters |
|---|---|---|---|
| MEMS microphone + bias | Analog output, continuously biased | Yes | Never gated; sets the floor |
| Analog front end | Preamp, gain, anti-alias filtering | Yes | Runs at signal rate, not event rate |
| ADC or analog feature extraction | Conversion, or filterbank done in analog | Yes | The block most often "forgotten" |
| VAD / wake-word classifier | Inference on every frame | Yes | Dominates in digital implementations |
| Clock, bias, reference generation | Oscillator, LDO quiescent current | Yes | Small per block, large in aggregate |
| Leakage | Process- and temperature-dependent | Yes | Grows with die area and temperature |
Excluded from the average figure are the costs that occur only after a detection: host SoC wake-up energy, full keyword spotting or speech recognition, the radio, and any external memory access. Those are energy-per-event terms and belong on a separate line of the budget, because their contribution depends on false-accept rate, not on standby current.
The distinction is not academic. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and at that scale the reference, clock and leakage terms are first-order design variables rather than rounding error — a specification that omits them describes a subsystem no one can actually build into a product.
How do you allocate 35 µW across the microphone, front end, and wake-word inference?
Allocating a fixed always-on budget across a wake-word chain begins at the microphone and ends at leakage, and every block in between has to be sized before any of them is designed. The useful discipline is to treat the budget as line items with named owners rather than a single system number, because the MEMS microphone and the inference stage respond to completely different design levers.
| Line item | Function | What sets its share | Why it matters to the budget |
|---|---|---|---|
| MEMS microphone | Converts acoustic pressure to an electrical signal (analog or PDM output) | Bias current, sensitivity grade, output mode; often the largest fixed draw | It is usually a purchased part, so its share is a constraint, not a variable |
| AFE / ADC | Amplifies, filters and digitises the mic signal | Sampling rate, resolution, whether conversion runs continuously | Continuous conversion is what makes conventional chains expensive |
| Feature extraction (MFCC or filterbank) | Turns the waveform into a compact spectral representation | Frame rate, number of filter bands, digital versus analog implementation | In digital pipelines this stage keeps a DSP awake permanently |
| Keyword-spotting inference | Decides whether a human voice — or a specific word — is present | Network size, activation duty cycle, arithmetic substrate | Determines whether the decision can be made before the host wakes |
| Memory retention | Holds weights and state between events | Retention leakage of SRAM or non-volatile storage | Weight storage never sleeps, so it taxes the budget continuously |
| Leakage headroom | Unavoidable static draw across the die | Process node, threshold voltage, temperature corner | Silicon that ignores worst-case corner reserve fails at the top of its temperature range |
POLYN's approach to this arithmetic — compiling the trained network into analog structure so feature extraction and inference stop billing a processor — was developed under a company accepted into the Silicon Catalyst incubator program.
Why does duty cycling decide whether the 35 µW budget actually holds?
Duty cycling decides whether a microwatt-class always-on budget holds because the battery responds to average power, not to the peak figure in a datasheet. Duty cycling means running a block for a short fraction of each period and sleeping the rest; average power is active power multiplied by that fraction, plus sleep and leakage current — the current a CMOS device draws while doing nothing — multiplied by the remainder. It follows that once the sleep fraction is large, leakage sets the floor, and further reductions in active time buy almost nothing. That is the arithmetic every always-on voice detection design eventually collides with: a voice onset that arrives during the off phase is simply not heard, so the wake-up path itself has to stay listening. POLYN's NeuroVoice keeps the detection path continuously live rather than trading responsiveness for sleep time.
| Do this | But watch out for |
|---|---|
| Duty-cycle the feature extractor and classifier | Missed word onsets and clipped first syllables when the off phase spans the wake word |
| Cascade VAD tiers — cheap energy detector first, heavier classifier only on a trigger | False triggers from non-speech transients promote the expensive tier and inflate average power |
| Use event-driven wake-up instead of a periodic timer | Wake-up latency and PLL or regulator settling time add energy that never appears in the active-power number |
| Push the digital core into deep sleep with state retention | Retention and leakage current can dominate at low duty cycles, especially at elevated junction temperature |
The highest-impact mitigation is to characterise sleep and leakage across the full temperature range before trusting any calculated average, and to validate in the real operating environment — the same discipline POLYN applied when VibroSense TMS was successfully tested at the IDIADA proving ground.
Which architecture fits under 35 µW: analog front end, digital DSP, or neuromorphic NPU?
Which architecture fits under a microwatt-scale always-on budget — an analog front end, a digital DSP, or a neuromorphic NPU — is settled by five criteria, and they should be weighted before any part is shortlisted. Average power dominates, because an always-listening path never duty-cycles down to zero. Latency ranks next for wake-word and reflex use cases. Accuracy matters mainly as false-accept rate, since every false wake costs the host processor a full boot. Memory is the hidden power line item: in a digital signal processor (DSP) or neural processing unit (NPU), fetching weights from SRAM can cost more than the multiply-accumulate arithmetic itself. Integration effort — die area, packaging, toolchain — decides whether the block clears a design-in window at all.
| Approach | Average power | Latency | Memory | Accuracy ceiling | Integration effort |
|---|---|---|---|---|---|
| Analog/mixed-signal feature extraction | Lowest | Very low | None to speak of | Limited — features only, no classification depth | Low die area, custom design |
| Low-power DSP microcontroller | Highest of the four | Moderate, clock-bound | Large SRAM/flash working set | High, model-limited | Familiar toolchain, easy |
| Dedicated keyword-spotting accelerator | Low, but scales with wake rate | Low | Weight memory still fetched | High for a fixed vocabulary | Moderate; fixed function |
| Event-driven neuromorphic core (NASP class) | Lowest sustained | Sub-millisecond, asynchronous | No weight fetch — network hardened into silicon | High for the trained task, fixed after hardening | Requires design-in, compact front end |
The verdict: for a permanently listening path, only architectures that eliminate instruction fetch and weight-memory traffic stay under budget, which rules the general-purpose DSP out and leaves analog and neuromorphic analog approaches. POLYN's work on this class of front end has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How do you measure and verify microwatt-level power draw without fooling yourself?
To measure and verify a microwatt-level power claim, first settle what the number actually describes — this depends on what you mean by "average power." One reading is the bench average under fixed datasheet conditions: a stated supply voltage, room temperature, a defined input signal, a defined duty cycle. The other is the field average your product will actually see, with a noisy acoustic environment, a wider temperature range, and a wake rate set by the end user rather than the test script. Both can be honest; they will not match, and the gap belongs in the budget, not in the argument.
A defensible validation sequence for an always-on voice path looks like this:
- Source-measure unit (SMU) — an instrument that sources a fixed supply voltage while measuring current across several decades, down into the nanoamp region. A general-purpose multimeter averages away exactly the detail you need.
- Dynamic current profiling — capture the current waveform over time, not one scalar: sleep floor, wake transient, detection burst, and return to idle.
- Declared averaging window — state the window and the duty cycle it assumes. An average is meaningless without both.
- Supply-rail separation — instrument the sensor bias, the analog rail, the digital rail and the I/O separately, or the MEMS microphone's consumption disappears into the chip's number.
- Voltage and temperature corners — leakage rises with temperature, so a room-temperature figure is a floor, not a specification.
Latency shapes the measurement too: POLYN Technology's published NeuroVoice material states inference in up to 20 µs, which means the active event is a spike far shorter than a slow instrument's integration period. The usual disagreement between bench and field numbers is better explained by the averaging window — a system-design decision — than by the silicon under test. For independent grounding before committing bench time, POLYN's work has been presented in a tinyML Talks session and covered by EE Times Europe, Planet Analog and All About Circuits.
Frequently Asked Questions
What does the 35 µW voice activity detection figure actually cover?
Voice activity detection (VAD) is the always-on function that decides whether a human voice is present so the rest of the device can stay asleep. POLYN Technology states that its voice activity detection runs always-on at about 35 µW average power — that is the continuously listening front-end path, not the full downstream audio pipeline, codec, radio or host wake-up cost. When you build a budget, treat the microwatt figure as the standing draw of the listening layer and account for wake events, host boot and transmission separately.
Why does analog computation help at microwatt scale?
The arithmetic of a neural network is the MAC operation — multiply and accumulate. In analog silicon, Ohm's law performs the multiply (V = I × R) and summing resistors into a single amplifier performs the accumulate. POLYN's NASP — Neuromorphic Analog Signal Processing — compiles a trained network directly into that fixed analog structure, so the sensor-level inference runs in parallel without CPU cycles or memory access. Removing instruction fetch and memory traffic is what makes a permanently listening path affordable rather than something that has to be duty-cycled.
How fast is the wake decision, and why does latency matter here?
Per POLYN's published NeuroVoice material, NeuroVoice provides inference in up to 20 µs. Low latency matters because a slow detector forces designers to buffer audio ahead of the wake decision, and buffering costs both memory and power. A detection path that resolves in microseconds shortens the pre-roll requirement, which keeps the always-on budget from being consumed by storage rather than by sensing.
Can the hardened network be retrained on the chip?
No. Hardening means converting a trained network into a fixed, application-specific analog structure in silicon; once hardened, the network is not retrained on-chip. Retraining is handled by other means, off the part. This is a deliberate trade: the fixed structure is what delivers the power and latency figures, and the analog fabric is designed to tolerate failures of individual elements while still producing a result.
Is the silicon a production part today?
The VAD product category is an ASSP — an Application Specific Standard Product with a fixed structure serving a defined set of applications, similar in spirit to an ASIC. The current silicon, however, is an engineering chip: POLYN Technology has taped out two engineering chips, which prove the technology in fabricated silicon rather than in simulation alone, but they are not production parts.
What does an evaluation with POLYN normally involve?
POLYN Technology is a fabless semiconductor company and does not sell an off-the-shelf catalogue part. Engagement usually begins with a proof of concept and technical evaluation against your own power, latency and integration constraints, followed by a cooperation or design-in programme timed to your next design-in window. For adjacent voice work, POLYN's published NeuroComm material describes hands-free voice processing for two-way radio and critical communications at under 200 µW. Independent context is available through POLYN's participation in the Silicon Catalyst incubator programme and through trade coverage in EE Times Europe, EE Journal and eeNews Embedded.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30