At a glance
- Budget an always-on node by allocating microwatts to the wake stage first, then to detection, then to the host processor.
- POLYN's voice activity detection runs always-on at about 35 µW average power, keeping the wake stage inside a microwatt-scale envelope.
- NeuroVoice provides inference in up to 20 µs, so low power does not have to cost response time.
- NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead from sensor-level computation.
- POLYN has taped out two engineering chips — silicon evidence, not simulation only.
POLYN
Published:
Budgeting microwatts across an always-on sensor node starts with a simple allocation rule: the stage that never sleeps gets the smallest share, and everything downstream is gated behind it. Split the node into three tiers — the permanently-on wake stage, the event-triggered detection or classification stage, and the host processor that only runs when the earlier tiers say something happened — then assign an average-power ceiling to each tier before choosing any part. POLYN Technology's voice activity detection, the always-on check for whether a human voice is present, runs at about 35 µW average power, which is the kind of figure the wake tier has to hit if a device is expected to listen permanently rather than duty-cycle its way around the problem.
The second constraint architects usually discover late is that the wake tier's power number and its response time are coupled. Cutting current by slowing the front end pushes latency into the detection tier and, eventually, into the user experience. NeuroVoice provides inference in up to 20 µs, per POLYN's published product specification, and operates within an ultra-low-power product envelope below 150 µW — which is why the two budgets, microwatts and microseconds, should be drawn on the same sheet rather than negotiated in sequence. The mechanism behind that pairing is NASP (Neuromorphic Analog Signal Processing), POLYN's approach of compiling a trained neural network directly into analog silicon so the computation runs in parallel, asynchronously, with no CPU cycles and no memory access to pay for. This article walks through how to build that budget line by line in 2026, where the microwatts actually go, and how a neuromorphic front-end chip next to the sensor changes the arithmetic.
How do you calculate a microwatt power budget for an always-on sensor node?
To calculate a microwatt budget for an always-on sensor node, work from average power, not peak power: the governing expression is P_avg = V_supply × I_avg, where I_avg is the duty-cycle-weighted blend of active and sleep current. Expand it as I_avg = D × I_active + (1 − D) × I_sleep, with duty cycle D = t_active / t_period. When the node is event-driven rather than periodically sampled, the equivalent form is more useful: P_avg = (V_supply × I_active × t_active) × f_event + P_sleep, so energy per event and event rate — not clock speed — set the number you must defend.
Which attributes belong in the budget sheet?
| Attribute | Typical range or values | Why it drives the result |
|---|---|---|
| Supply voltage (V_supply) | Regulated rail or raw cell voltage | Scales every term linearly; a rail chosen for the radio penalises the sensing path |
| Active current (I_active) | Datasheet operating current per block | Dominates when duty cycle is high or wake-ups are frequent |
| Sleep / leakage current (I_sleep) | Retention and leakage current | Becomes the floor once duty cycle falls; sets the best case you can ever reach |
| Duty cycle (D) | 0 to 1, or event rate × t_active | The single lever most architects over-trust |
| Wake-up latency and settling time | Oscillator, bias and ADC settling | Adds silent active time that never appears in the duty-cycle assumption |
| Source budget | Battery capacity × voltage over target life, or harvester sustained output | Converts the power figure into a lifetime, which is what the design-in review actually asks for |
A permanently listening or sensing requirement pushes D toward 1, at which point the only remaining lever is the energy cost per inference in the silicon that performs it. That is the layer POLYN and Fraunhofer Mikroelektronik addressed jointly when they designed ultra-low-power Tiny AI NASP chips together, NASP being POLYN's neuromorphic analog signal processing technology.
Which subsystems actually consume the microwatts in a duty-cycled node?
This section narrows the scope to one case: a battery-powered node that spends most of its life asleep. In that regime, the subsystems that actually consume the average budget are rarely the ones that dominate the datasheet — a duty-cycled design pays for standing current far more than for peak current, because peak current is billed only for the fraction of time the part is awake.
The five recurring line items, each with the attribute that determines its contribution:
- MCU sleep state. Attribute: which retention mode is selected (deep sleep with RAM retention, standby, or full stop). Range spans several orders of magnitude across modes. Matters because the sleep mode chosen at architecture time sets the floor no firmware optimisation can cross.
- Real-time clock (RTC). Attribute: oscillator type and wake cadence. Always energised by definition, so it is a constant draw, not a duty-cycled one — small in absolute terms, but permanent.
- Sensor front end. Attribute: sampling rate, bias current, and whether the analogue chain can be gated between samples. This is the line item POLYN's neuromorphic front-end chip is designed to sit inside — a chip that pre-processes raw sensor data with a neural network next to the sensor, before the host processor is woken at all.
- Radio transmit burst. Attribute: payload size and transmissions per hour. Its average contribution is energy-per-bit multiplied by traffic, which makes data volume the real control lever.
- Regulator quiescent current. Attribute: the converter's own standing draw, plus light-load efficiency. Matters because it is charged against every microamp the rest of the node saves.
POLYN, a fabless semiconductor company working at this sensor edge, was accepted into the Silicon Catalyst incubator program.
How do MCU sleep modes compare when the node must stay always on?
MCU sleep modes trade residual current against wake latency, and for a node that must stay always on, that trade decides the whole power budget. Before comparing the modes, fix the evaluation criteria and their weighting:
- Residual power in the resting state — the dominant term, because an always-on node spends nearly all of its time here.
- Wake latency — time from trigger to first valid sample; weight this second, since a slow wake means the opening of the event is lost.
- State retention — whether SRAM and register contents survive, which sets how much re-initialisation energy each wake costs.
- Wake-source granularity — what can actually raise the interrupt: a real-time clock (RTC) alarm, a GPIO edge, or an analog comparator threshold. This criterion decides how many false wakes the node pays for.
| Mode | Residual power | Wake latency | State retained | Practical wake source | Main trade-off |
|---|---|---|---|---|---|
| Deep sleep / power-down | Lowest | Longest — full clock and PLL restart | Little or none | External pin edge | Cheapest at rest, most expensive per wake |
| Stop mode with RAM retention | Low, but retention current is continuous | Short | SRAM and registers | Pin, RTC, comparator | Retention current never stops accruing |
| Standby with RTC | Very low | Moderate | Backup domain only | Scheduled RTC alarm | Time-driven, so real events between alarms are missed |
| Wake-on-interrupt peripheral | Higher — an analog block stays biased | Shortest | Depends on host mode | Comparator or threshold detector | Wakes on amplitude, not on meaning |
Weighting the criteria this way exposes the real limitation: no sleep mode answers the question of whether an event matters. A threshold comparator fires on any loud transient; an RTC alarm samples whether or not anything happened. POLYN moves that decision next to the sensor, where a neuromorphic front-end chip — a chip that pre-processes raw sensor data with a neural network before the host sees it — evaluates the signal continuously in analog and hands the MCU a qualified trigger, letting the host stay in its deepest retention mode. POLYN's VibroSense TMS, which applies this principle inside the tire, was successfully tested at the IDIADA proving ground.
Which energy source fits a microwatt budget: coin cell, supercapacitor, or energy harvester?
Which energy source fits a microwatt budget depends on four criteria, and they should be weighted before any cell or harvester is short-listed. Sustained average power is the first: what the source can deliver continuously without the node browning out. Self-discharge or leakage — the current a store loses to internal chemistry or dielectric losses even when the node is idle — matters more than raw capacity, because at microwatt draw the leakage can rival the load. Service life under the enclosure's thermal and mechanical conditions comes third, since a sealed module is rarely serviceable. Cost and integration burden ranks last for feasibility but usually decides the design-in.
| Source | Sustained microwatt budget | Self-discharge / leakage | Service life | Cost and integration |
|---|---|---|---|---|
| Primary lithium coin cell | Modest but predictable; poor at peak current | Low | Fixed; ends when depleted | Low cost, trivial to integrate |
| Rechargeable cell | Higher, if a charge path exists | Higher than primary chemistry | Limited by cycle count and temperature | Adds charger and protection circuitry |
| Supercapacitor | Poor as a primary store; excellent for peaks | Highest of the four | Very long cycle life | Bulky per unit of energy stored |
| Photovoltaic or thermoelectric harvester | Highly variable with light or thermal gradient | Not applicable; no stored charge | Indefinite while the gradient exists | Needs a buffer store and a power-management IC |
The store and the harvester answer different questions. A harvester sets the long-run average available to the node; a coin cell or supercapacitor covers the transients that the harvester cannot supply on demand. The practical consequence is that the always-on processing stage's average draw, not its peak, decides which column a design can live in — which is why the continuous compute budget is the real gating item rather than the cell chemistry. POLYN's work on that sensor-edge budgeting problem has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
What are the risks of cutting sampling rate versus cutting transmit rate?
Cutting the sampling rate and cutting the transmit rate both reclaim microwatts, but the risks they create are not symmetric — one degrades the signal itself, the other only delays it. Reducing sampling means the sensor observes the world less often (duty-cycling: waking the acquisition path periodically instead of running it continuously), so transient events that fall between windows are gone permanently. Reducing transmit rate keeps the observation intact and moves less of it off-chip.
| Dimension | Cutting sampling rate | Cutting transmit rate |
|---|---|---|
| What is saved | Analog input and converter power | Radio and interface power, usually the larger draw |
| Data-quality risk | Aliasing and missed transients; unrecoverable | Signal preserved; only timeliness is traded |
| Reliability risk | Event detection becomes probabilistic across duty cycles | Buffer overflow and loss if local storage is undersized |
| Recoverability | None — the sample was never taken | High — data can be re-sent or re-aggregated |
| Latency effect | Worst-case response bounded by the sleep interval | Response bounded by the batching window |
Do and watch out
- Do reduce transmit rate first, since the link is typically the dominant consumer. But watch out for batching windows that push worst-case event latency past the system's reaction deadline.
- Do duty-cycle the acquisition path where the phenomenon is slow and stationary. But watch out for rare, short-lived transients — vibration impulses, speech onsets — that the sleep interval erases.
- Do aggregate on-device so the radio carries features rather than raw samples. But watch out for aggregation that discards the exact feature a later model revision will need.
The mitigation for the highest-impact risk — missed events — is to keep observation continuous and move the decision next to the transducer. POLYN's NeuroVoice takes that route: the classification happens in analog silicon on the continuously observed signal, so the host is woken only when the event is already confirmed.
How do you measure and verify microwatt-level current draw on real hardware?
This depends on what you mean by measuring and verifying microwatt-level draw: an averaged energy-per-hour figure over a long window, or the instantaneous current profile through a wake event. The two interpretations demand different instruments, and conflating them is where most disputed numbers originate.
For average power over minutes or hours, a coulomb counter or a source-measure unit (SMU — a bench instrument that sources a voltage and measures the resulting current on the same terminals) integrating charge is adequate. For transient behaviour — the microamp-to-milliamp step when an always-on detector wakes the host — you need a dynamic current analyzer or a shunt-plus-instrumentation-amplifier chain with enough bandwidth and dynamic range to catch both floors and spikes.
| Do this | But watch out for |
|---|---|
| Use an SMU for quiescent floor measurement | Ranging discontinuities as the instrument autoswitches |
| Add a shunt plus amplifier for fast edges | Burden voltage on the shunt browning out the DUT |
| Log with a coulomb counter for long windows | Leakage in probes, cabling and unused I/O pulled into the total |
| Report average and peak separately | Averages that quietly hide a duty-cycled wake cost |
A reasonable reading of recurring measurement disputes is that the harness, not the silicon, usually decides whether a microwatt claim survives design review. POLYN Technology states its always-on voice activity detection runs at about 35 µW average power — a figure of that order only means something alongside a stated averaging window and load condition.
Mitigation tip: measure the always-on block on its own dedicated supply rail, against a known clean reference, before attributing anything to the system total.
Frequently Asked Questions
How do you budget microwatts across an always-on sensor node?
Budgeting microwatts across an always-on sensor node means allocating a fixed average-power envelope — not a peak figure — across four consumers: the sensor bias and analog front end, the detection or wake stage that runs continuously, the host processor that only wakes on a trigger, and the radio or link that moves data off the node. The always-on stage dominates because it never sleeps, so it should be sized in microwatts and the duty-cycled stages in milliwatts. A practical rule is to fix the always-on allowance first, then let it constrain everything downstream, rather than budgeting the wake path last.
What is NASP, and what does it remove from the power budget?
NASP — neuromorphic analog signal processing — is POLYN's core technology: a trained neural network compiled directly into analog silicon, so the computation runs in true parallel asynchronous mode. The multiply-accumulate arithmetic of the network is performed by physics rather than instructions, with Ohm's law doing the multiply and summed currents into an amplifier doing the accumulate. Because the network is fixed in silicon, POLYN's NASP architecture removes CPU cycles and memory accesses from sensor-level neural-network computation — and memory traffic is usually the largest line item in a digital always-on path.
Why does a sensor front-end reduce data volume as well as power?
Moving raw samples costs energy in the link and in the host that has to parse them. A neuromorphic front-end chip — a chip that pre-processes raw sensor data with a neural network next to the sensor, before it reaches the host — sends compact embeddings instead of waveforms. POLYN states that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, and POLYN's VibroSense IIOT reduces vibration data volume by 1,000–4,000 times at the sensor edge according to the product's published description. That reduction relieves the radio budget, not just the compute budget.
How much latency does an always-on detection stage add?
Per POLYN's published NeuroVoice specification, NeuroVoice provides inference in up to 20 µs — fast enough that the detection decision is not the limiting element in a wake-on-voice chain. This matters because in conventional digital nodes, saving power usually means slowing the sampling or detection loop and paying for it in responsiveness. POLYN's always-on voice detection is designed so the architect does not trade one budget against the other.
Which POLYN products map to which always-on power envelope?
- NeuroVoice — voice activity detection for wake-on-voice and single-microphone voice extraction; POLYN Technology states its voice activity detection runs always-on at about 35 µW average power, within a product envelope below 150 µW per the NeuroVoice product page.
- NeuroComm — hands-free voice processing for two-way radio and critical communications at under 200 µW, per POLYN's critical-communications paper.
- VibroSense TMS — reports peak friction coefficient, the grip available at the tire-road contact, across the 0–1 range in 0.1 steps, measured directly inside the tire; it was successfully tested at the IDIADA proving ground.
- NeuroSense — a robotics reflex layer in research phase under a joint project, not an available product.
What maturity is POLYN's silicon at in 2026?
POLYN has taped out two engineering chips — fabricated test chips that prove the technology in silicon, not production parts. The VAD product category itself is an ASSP, an application-specific standard product with a fixed structure serving a defined set of applications. The network is hardened, meaning it is fixed into analog structure at design time and is not retrained on-chip; updates are handled by other means. POLYN designed ultra-low-power Tiny AI NASP chips together with Fraunhofer Mikroelektronik and was accepted into the Silicon Catalyst incubator program. Engagement starts with a proof of concept, not an off-the-shelf order.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30