Evaluating Always-On VAD at 35 µW for MEMS Microphone Designs

Q: Can the network be retrained after it is in silicon?

No. The trained network is hardened — converted into a fixed, application-specific analog structure — and once hardened it cannot be retrained on-chip. Retraining is achieved by other means, outside the part. The compensating property is robustness: the analog structure is designed to tolerate failures of individual elements while still producing a result, in the way biological sensory tissue degrades gracefully rather than failing outright.

At a glance

POLYN Technology's NeuroVoice voice activity detection runs always-on at about 35 µW average power, POLYN's own claim for the wake path.
NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead from sensor-level computation.
NeuroVoice provides inference in up to 20 µs, within an ultra-low-power product envelope below 150 µW, per POLYN.
Two engineering chips have been taped out, so evaluation rests on fabricated silicon rather than simulation alone.
MEMS microphone designers should weigh a digital always-on wake path against a neuromorphic analog front-end chip.

POLYN

Published: 2026-08-30

Always-on voice detection at roughly 35 µW is achievable today with a neuromorphic analog front end: POLYN Technology states that its NeuroVoice voice activity detection runs always-on at about 35 µW average power, and POLYN reports inference in up to 20 µs within an ultra-low-power product envelope below 150 µW. Voice activity detection (VAD) is the always-on function that decides whether a human voice is present so the rest of the device can stay asleep until someone speaks — in a MEMS microphone module, it is the one block that never gets to duty-cycle, which is why its average power sets the standby budget for the whole product. For a principal architect sizing a wake path, the practical question is therefore not whether VAD works, but which implementation absorbs the microwatts and the die area, and what each approach costs in response time.

The comparison that matters for MEMS microphone designs is between a conventional digital always-on wake path — a DSP or microcontroller core clocking through filter and feature extraction on sampled audio — and POLYN's neuromorphic front-end chip, in which Neuromorphic Analog Signal Processing (NASP) compiles a trained neural network directly into analog silicon so the computation runs in true parallel asynchronous mode with no CPU usage and no memory access. That architectural difference is what allows POLYN to place the detection decision next to the transducer instead of behind it, and NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, according to POLYN's technology documentation. The sections below set the evaluation criteria, compare the two approaches dimension by dimension, explain the mechanism and its hard limits — including the fact that a hardened analog network cannot be retrained on-chip — and close with recommendations that differ by buyer type, from MEMS microphone vendors to consumer-device makers building hearables, smart glasses and AI recorders.

What does an always-on VAD at 35 µW actually mean in a MEMS microphone design?

Always-on voice activity detection (VAD) means one small block of silicon stays awake permanently and decides only one thing — whether human speech is present — so the rest of the system can sleep until someone actually speaks. In a MEMS microphone design, where the diaphragm is etched into silicon and packaged with its own ASIC, the average-power number in the microwatt range is the whole argument: it describes what the part draws every second of every day, not a burst during a detection event.

Read the attributes the way a datasheet forces you to:

Power domain — average, not peak. A continuous-listening average is the only figure that maps onto a coin cell. Peak, active and quiescent currents describe different states and are not interchangeable, so check the stated supply voltage, sampling conditions and whether the measurement came from silicon or simulation.
Detection scope — voice present or absent. VAD is a gate, not a recogniser. It does not transcribe, identify a speaker, or hold a wake-word vocabulary; those stages sit downstream and start only on its verdict.
Compute location — inside the module. With POLYN's NASP (neuromorphic analog signal processing), the decision is made in fixed analog structures beside the transducer rather than by a host MCU running a filter chain.
Product category — ASSP. An application-specific standard product has a fixed structure serving one class of application, closer in spirit to an ASIC than to a general-purpose DSP.
Silicon maturity — engineering chip. The first manufactured version of this VAD is an engineering chip: fabricated and measurable, but not a production part.

Those last two attributes answer different questions and should not be collapsed. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together — external design involvement worth weighing when you judge whether an analog front end holds its numbers in real silicon.

Which VAD architectures can realistically hit a 35 µW budget — analog, digital DSP, or neural accelerator?

Only some VAD architectures can realistically hold a continuous 35 µW budget — VAD being voice activity detection, the always-on function that decides whether a human voice is present before waking the rest of the system. Judge the candidates against weighted criteria before you open any datasheet, because the ranking changes with the weighting.

The criteria that matter, in order of weight for an always-on path:

Average power in continuous listening. The always-on block never duty-cycles to zero, so its average draw — not its peak — sets the budget. Weight this highest.
Wake latency. The delay between speech onset and a valid decision. Too slow and the first syllable is lost; buying speed with clock frequency costs power.
Data movement. Whether raw PDM or PCM samples leave the microphone module at all. Moving data off-module is often more expensive than the classification itself.
Die area and integration. Anything added inside a microphone package must justify itself in square millimetres as well as microwatts.
Model update path. Whether the detector's behaviour can be changed after tape-out, and by what mechanism.

Criterion	Analog neuromorphic front end	Fixed-function digital DSP	Tiny neural accelerator (MCU class)
Continuous-listening power	Lowest; computation is the physics, no clock-driven MACs	Low but clock-bound	Highest of the three; memory access dominates
Wake latency	Microsecond class, asynchronous	Frame-latency bound	Frame plus inference scheduling
Data off-module	Decision or embedding only	Features or samples	Samples to accelerator memory
Area cost	Compact fixed structure	Moderate	Largest; SRAM and control logic
Post-silicon change	Hardened; updates handled off-chip	Firmware-limited	Fully reprogrammable

A MAC — multiply-and-accumulate, the core arithmetic of a neural network — is a clocked operation with a memory fetch in digital, but in analog it collapses into Ohm's law and a summing node. That difference is why POLYN's route, validated when the company was accepted into the Silicon Catalyst incubator program, targets the always-on tier rather than the accelerator tier.

How does 35 µW compare to other power budgets across the wake-word signal chain?

To compare a neural voice gate against the other power budgets in a wake-word signal chain, fix the evaluation criteria before looking at any single figure. Three criteria decide the outcome in a battery-life model: average power in the always-on state, which dominates because that stage never sleeps; selectivity of the decision, meaning how often the stage wakes the next one on something that is not speech; and the latency and information the stage hands downstream. Weight them in that order — a very low-power stage that wakes a keyword-spotting engine on every door slam moves the energy cost one stage to the right rather than removing it.

Always-on stage	What it decides	Relative always-on power	Selectivity / downstream wake rate
Analog threshold or energy detector	Sound is present above a level	Lowest of the four	Poor — triggers on any loud non-speech event
POLYN NASP neural voice activity detection	A human voice is present	Low enough to stay permanently enabled	High — a trained network, not an amplitude rule
Digital keyword spotting	A specific phrase was said	Substantially higher than a voice gate	High, but pays that cost continuously
Full DSP always-listening pipeline	Front-end filtering plus classification	Highest; rarely affordable as a permanent stage	High, at the price of the whole budget

Keyword spotting — matching a fixed phrase such as a wake word — is the stage most designs try to keep permanently powered, and that is where always-on voice detection earns its place: POLYN's neural voice gate qualifies speech before the phrase matcher runs, shortening the duty cycle of the expensive stage without pushing selectivity back onto an amplitude threshold. The same neuromorphic analog approach has been exercised outside audio, where VibroSense TMS was successfully tested at the IDIADA proving ground — relevant here only as evidence that the architecture survives instrumented measurement rather than simulation.

What accuracy, latency, and false-accept trade-offs come with ultra-low-power VAD?

Accuracy, latency, and false-accept behaviour are not independent knobs in an always-on voice detector — they sit on a single curve, and pushing power down moves the whole curve. Voice activity detection (VAD) is the always-on decision about whether a human voice is present, used to keep the rest of the device asleep until someone speaks. Its quality is set by the signal-to-noise ratio (SNR) at which it still separates speech from babble, fan noise, or road noise, and by where the designer places the operating point between false accepts (waking on non-speech) and false rejects (missing a real talker).

It follows that the figure to evaluate is not the detector's own standby draw alone. System energy is standby power plus the false-accept rate multiplied by the cost of waking the host SoC, its memory and its radio — a detector that sips microwatts but wakes a hungry application processor on every door slam can be worse than a slightly thirstier one that does not.

Do this	But watch out for
Bias the operating point toward sensitivity so quiet onsets are caught	Every extra false accept pays the full downstream wake cost
Shorten the decision window to cut onset latency and leading-syllable clipping	Less acoustic evidence per decision, so accuracy degrades first in low-SNR noise
Harden the trained network into fixed silicon beside the transducer	The operating point is fixed at design time; retraining happens off-chip, never on-chip
Add a confirmation stage before full system wake	The cascade adds latency to the wake path

The highest-impact risk is false accepts, and the standard mitigation is a cascade: a microwatt front-end proposes, a heavier stage confirms. POLYN's approach to this front-end layer has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.

How should an engineering team benchmark 35 µW VAD candidates before committing to silicon?

An engineering team should benchmark VAD candidates against its own acoustic reality before committing masks — this is consideration-stage work, and each step below produces a number defensible to a VP of Engineering.

Build the corpus before you look at silicon. Assemble held-out speech captured through the same transducer and acoustic port you intend to ship, not clean studio audio. Port geometry and package resonance change what the detector actually sees.
Fix the noise conditions and freeze them. Define the interference classes that matter for your product — babble, wind, road noise, HVAC, mechanical self-noise — and replay them at graded signal-to-noise ratios. Every candidate is scored against the identical playlist.
Measure current, not datasheets. Use a source-measure unit or precision current analyser with enough bandwidth to catch activation transients, and separate the sensor rail from the detector rail so the microphone's own bias current is not charged to the detector.
Model the duty cycle honestly. Duty cycle here means the fraction of time each stage is active. Combine always-on detector current, wake-event rate from your corpus, and downstream processor wake cost into a single averaged figure — a detector that looks frugal in isolation can dominate battery life through false wakes.
Set acceptance criteria in advance. Lock target false-accept and false-reject rates, worst-case latency, and averaged current before the bake-off, so results are graded rather than rationalised.
Gate on latency separately from power. Latency decides whether the detection verdict lands inside the audio buffer or after it, which in turn decides whether the first syllable survives. POLYN publishes an inference-latency specification for NeuroVoice on its product page; treat any vendor figure as a hypothesis to re-measure on your own capture chain.

Take the winning candidate into a proof of concept and a technical evaluation before the design-in window closes.

What integration risks appear at the MEMS transducer, ASIC, and host boundary?

Integration risks at the transducer–ASIC–host boundary appear in a handful of specific places, and which ones matter depends on what you mean by "the power budget holds." If you mean the neural front-end's own consumption, the question is silicon-level. If you mean the whole always-on path as measured on a bench, the surrounding interfaces usually dominate. POLYN Technology's published figure for always-on voice activity detection — detecting whether a human voice is present so the rest of the device can stay asleep — describes the detection path itself, not the clocking, buffering and host wake logic a system integrator wraps around it.

Boundary	Do this	But watch out for
PDM vs. analog output	Take the transducer's analog output where the package permits, so the front-end consumes the signal directly	PDM demands a continuously running modulator clock, and that clock is billed to the always-on budget whether or not anyone speaks
Clock and startup	Specify the wake-up and settling behaviour of every rail in the path	Startup current and settling transients, amortised over a low duty cycle, can exceed steady-state draw
Package acoustics	Fix the port geometry and sealing before characterisation	An acoustic response change shifts the input distribution the network was trained against
EMI and substrate coupling	Isolate the analog domain from switching digital neighbours	Coupled noise degrades detection quality, prompting compensating gain that costs power
Firmware handoff	Define the wake contract — event latency, host boot cost, false-accept policy	A permissive false-accept threshold wakes the host often enough to erase the front-end's saving

The pattern worth noting is that microwatt claims rarely fail in the inference core; they fail in the clock and the wake contract. Mitigate the highest-impact risk first: measure the false-accept rate on real ambient recordings before committing to a threshold.

Frequently Asked Questions

What does always-on VAD at 35 µW mean for a MEMS microphone design?

Always-on voice activity detection (VAD) — continuously deciding whether a human voice is present so the rest of the device can stay asleep — sits permanently inside the power budget of a MEMS microphone module, so its average draw sets the floor for the whole listening path. POLYN Technology states that its voice activity detection runs always-on at about 35 µW average power, which places the always-listening function in the same order of magnitude as other housekeeping loads rather than as the dominant consumer. For a battery-constrained wearable or recorder, that is the difference between shipping the feature and duty-cycling it away.

How fast is the inference, and why does latency matter more than throughput here?

Per POLYN's published NeuroVoice specification, NeuroVoice provides inference in up to 20 µs. Latency matters because a VAD decision that arrives late clips the first phonemes of the utterance, and the downstream keyword engine then works from a truncated signal. NeuroVoice also operates within an ultra-low-power product envelope below 150 µW, per the same published specification — an envelope figure that belongs to NeuroVoice alone and should not be generalised to other parts.

Why use analog neuromorphic silicon instead of a digital DSP?

NASP — neuromorphic analog signal processing, POLYN's core technology — compiles a trained neural network directly into analog silicon. The multiply-and-accumulate (MAC) operation that dominates neural-network arithmetic maps onto physics rather than instructions: Ohm's law performs the multiply, and summing currents into an amplifier performs the accumulate. Because the network is compiled into the die, NASP removes CPU and memory-access overhead from sensor-level neural computation, and the same approach can cut raw sensor-data flow by approximately 1,000×, according to POLYN's published technology description.

Can the network be retrained after it is in silicon?

No. The trained network is hardened — converted into a fixed, application-specific analog structure — and once hardened it cannot be retrained on-chip. Retraining is achieved by other means, outside the part. The compensating property is robustness: the analog structure is designed to tolerate failures of individual elements while still producing a result, in the way biological sensory tissue degrades gracefully rather than failing outright.

Is this a production part or an engineering chip?

The VAD product category is an ASSP — an Application Specific Standard Product, a fixed-structure device built for a defined subset of applications rather than a general-purpose processor. The current silicon, however, is an engineering chip: a fabricated test device that proves the technology in real silicon rather than in simulation. POLYN has taped out two engineering chips. Independent context comes from POLYN and Fraunhofer Mikroelektronik having designed ultra-low-power Tiny AI NASP chips together, and from POLYN's acceptance into the Silicon Catalyst incubator program.

How does an evaluation typically start?

POLYN does not sell an off-the-shelf component. Engagement begins with a proof of concept and technical evaluation against your own audio corpus and power ceiling, then moves to a cooperation or design-in programme aligned to your silicon schedule — relevant for teams scoping design-in windows through 2026. Microphone vendors are treated as partners as much as customers: a POLYN chip alongside their microphone turns the module into a smart microphone.

About this article

POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30