At a glance
- An engineering chip proves a design works in fabricated silicon; a production part adds qualification, reliability data, supply and change-control commitments.
- Ask vendors which silicon the quoted numbers came from, and what changes between the test chip and the shippable part.
- POLYN Technology has taped out two engineering chips, and describes them as engineering chips rather than production parts.
- POLYN Technology's own claim: NeuroVoice voice activity detection runs always-on at about 35 µW average power.
- Match the maturity question to your gate: proof-of-concept teams and volume design-in teams need different answers.
POLYN
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An engineering chip is a fabricated test chip that proves a design works in real silicon — it is not a production part. A production part is silicon that has cleared qualification, reliability characterisation, production test coverage, and the supply and change-notification commitments a program manager needs before committing a bill of materials. Both are real silicon; only one carries a shipping guarantee, and conflating them is the fastest way to lose a design-in window. When a vendor quotes a power or latency figure, the first question is which of the two produced it, and the second is what changes between that silicon and the part you would eventually buy. POLYN Technology, a fabless developer of NASP — neuromorphic analog signal processing, in which a trained neural network is compiled directly into analog silicon — has taped out two engineering chips, and states plainly that they are engineering chips. Its own claim for the NeuroVoice voice activity detection function is about 35 µW average power, always-on. If you are assessing a neuromorphic front-end chip in 2026, the checklist below separates what the silicon has already demonstrated from what still sits ahead of it.
What exactly separates an engineering chip from a production part?
What exactly separates an engineering chip from a production part is not the circuit on the die but the qualification status attached to it — and this section narrows to that single distinction, leaving evaluation strategy and design-in timing aside. An engineering chip is fabricated test silicon that proves a technology works in a real process, at real corners, with real parasitics; a production part is silicon whose behaviour has been characterised, qualified and committed to over a supply lifetime. POLYN describes its fabricated NASP silicon — neuromorphic analog signal processing, meaning a trained neural network compiled directly into analog structures — as engineering chips, not production parts, and that distinction is the honest one to hold any vendor to.
The attributes worth interrogating, with their usual values and why each matters:
- Maturity grade. Values: engineering sample (ES), qualification sample (QS), production silicon (PS). Determines whether datasheet limits are measured or projected.
- Mask revision / stepping. Values: successive steppings, metal-only or all-layer. A metal-only revision is cheap and fast; an all-layer revision resets schedule and cost. Ask which one an open erratum would require.
- Marking convention. Values: ES-marked or lot-marked devices versus fully marked production parts with traceable date and lot codes. Governs whether a device may legally ship in a customer product.
- Test coverage. Values: bench characterisation on selected units versus full automated test across voltage, temperature and process corners. Decides how much of the distribution you have actually seen.
- Reliability qualification. Values: none, partial, or a completed programme covering life test, ESD and latch-up. Absent this, field lifetime is an assumption.
- Supply commitment. Values: sample-only, limited build, or a longevity commitment.
The practical consequence is straightforward: an engineering chip answers does the architecture work in silicon?, while a production part answers will every unit behave this way for years? Those are different questions, and a vendor that conflates them is telling you something.
Which questions should you ask a chip vendor before accepting engineering samples?
The questions to ask a chip vendor before signing for engineering samples depend on what the samples are meant to prove. Two readings sit behind the same phrase. In one, the samples are pre-production silicon of a part already on a path to qualification, and your questions concern maturity: stepping ID (the revision marker identifying which mask set the die came from), errata coverage, and test escape rates. In the other, the samples are an engineering chip — a fabricated test die that proves a technology works in silicon but is explicitly not a production part — and your questions concern architecture risk and the route to a qualified device. POLYN, for instance, labels its own fabricated silicon as engineering chips rather than production parts, which is the disclosure you want in writing from any early-stage supplier before a design-in decision.
| Do this | But watch out for |
|---|---|
| Ask for the stepping ID and the full errata sheet, not a summary | Errata written only against features the vendor tested; ask what was not exercised |
| Ask whether the datasheet is preliminary, advance, or final, and which parameters are characterised versus guaranteed | Typical-only values with no min/max limits over temperature and voltage corners |
| Ask for test coverage: wafer sort, final test, and which parameters are screened per unit | Bench-measured "golden sample" data presented as production screening |
| Ask about guaranteed lifetime, longevity commitment, and qual plan (HTOL, ESD, temperature grade) | An engineering die that will never be qualified in its current stepping |
| Ask what changes between this stepping and the intended production part | Silent process or PDK migration that invalidates your characterisation work |
The highest-impact risk is treating characterised behaviour as guaranteed behaviour. Mitigate it by writing the specific parameters your design depends on into the evaluation agreement, with the corner conditions attached, before the samples ship.
How do engineering chips and production parts compare on qualification, traceability, and warranty?
Engineering chips and production parts differ less in what the silicon computes than in what the supplier contractually guarantees around it, so weigh the criteria before reading any comparison. Four criteria carry most of the decision weight for a design-in: test flow (how each die is screened — bench characterisation on a sample versus automated test equipment on every unit), qualification (whether the part has passed AEC-Q100, the automotive stress-test specification, and the JEDEC reliability suite such as HTOL and temperature-humidity bias), traceability and change control (lot and wafer genealogy plus PCN — product change notification — obligations when a process or assembly site moves), and commercial terms (warranty, price and lead time). Weight qualification and change control highest for automotive or safety-adjacent programmes; weight test flow and lead time highest when the goal is a working prototype.
| Dimension | Engineering chip | Production part |
|---|---|---|
| Test flow | Characterisation on selected units; parameters explored, not guaranteed | Full production test on every die, screened to a datasheet limit |
| AEC-Q100 / JEDEC qualification | Not qualified; reliability data is preliminary | Qualified to the grade the programme requires, with a report |
| Lot traceability | Limited — often a single split lot | Wafer, lot and assembly genealogy retained |
| Warranty and PCN | Supplied for evaluation, typically without warranty or change notification | Warranted, with contractual PCN and end-of-life notice |
| Price and lead time | Small volumes, prototype-scale timing | Volume pricing and forecast-driven supply |
The practical consequence is that an engineering chip answers the physics question and a production part answers the supply question. Those two answers arrive on different schedules. A vendor can legitimately demonstrate that a measurement principle works on real hardware — on a bench, in a rig, or on a vehicle — long before the silicon has completed an automotive qualification flow, and neither claim substitutes for the other. Ask vendors to state them separately: what has been proven in fabricated silicon, and what has been qualified, traced and warranted for volume supply.
Why can a silicon stepping change break a design that already passed bring-up?
A silicon stepping — a revision of the mask set and physical implementation behind the same marketing part number — changes the device your firmware was validated against, so bring-up results earned on an earlier stepping do not automatically carry forward. That matters most when the part you evaluated was an engineering chip: a fabricated test chip that proves the technology works in silicon but is not a production part. It follows that your qualification evidence is bound to a stepping, not to a product name, and every re-spin reopens the file.
The mechanism is straightforward. A layout or process change shifts timing corners and analog characterization data; errata closed by a metal fix may be replaced by new ones; and register maps, default states and firmware entry points often move with the digital wrapper. Each of those individually can invalidate a passing test report.
| Do this | But watch out for |
|---|---|
| Ask for the stepping identifier and full errata list per revision | Errata "closed" in a datasheet may be closed by a workaround your firmware must implement |
| Request timing and characterization data across voltage and temperature corners | Engineering-silicon data is often typical-unit, not statistical across a production lot |
| Diff the register map and firmware interface between revisions | Silent default-value changes rarely appear in release notes |
| Price requalification into the design-in schedule up front | EMC, functional-safety and customer acceptance testing may all restart |
| Look for independent technical scrutiny of the vendor's approach | Trade coverage is visibility, not qualification data — POLYN's work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session |
The highest-impact mitigation is contractual: agree in writing which stepping your qualification applies to, and require change notification with sample availability before any revision reaches your line.
What documentation proves a part has truly reached production status?
This narrows to one concrete question: which documentation actually proves that a part has crossed from engineering silicon into production status. Ask for the artefacts below by name, and treat an evasive answer as the answer.
| Artefact | What it is | What it proves |
|---|---|---|
| PPAP package with signed PSW | Production Part Approval Process submission, closed by a Part Submission Warrant | The supplier's process — not just the die — is approved for series supply |
| Qualification report | Reliability results against the applicable JEDEC and automotive-grade IC qualification regimes (HTOL, temperature cycling, HAST, ESD/latch-up) | The part survives its stated temperature and lifetime envelope |
| Production datasheet | Revision-controlled, with no "preliminary" or "advance information" banner | Limits are characterised min/max over corners, not typical bench values |
| PCN and EOL policy | Process/product change notification and end-of-life notice procedure | Changes are communicated in advance, not discovered at incoming inspection |
| Longevity programme | A written availability commitment against the part number | Supply survives your platform's production life |
| CoC and lot/date codes | Certificate of Conformance plus traceable lot marking | A field failure can be traced back to a wafer lot |
An honest pre-production vendor will state plainly which of these does not yet exist. POLYN is at that stage: two engineering chips have been taped out — fabricated test silicon that demonstrates the neuromorphic analog signal processing architecture in a real process, explicitly not production parts.
What stands in for a PPAP before that point is measured silicon data you can reproduce yourself. Ask for the characterisation set behind every headline figure: test conditions, corner coverage, sample count, and the measurement method. Per POLYN's published NeuroVoice specification, the product provides inference in up to 20 µs — the kind of datasheet-class claim a design team should re-measure on its own bench during evaluation in 2026, rather than accept on paper.
When should a program switch from engineering chips to production parts?
This decision belongs to the consideration-to-decision stage of a design-in program, and the practical rule is that the switch from engineering silicon to production parts happens at the gate where design change stops being cheap. An engineering chip is a fabricated test die that proves the technology in silicon without being a production part; it is legitimate evidence early and inadequate late. Map the gates before committing a slot on the schedule.
- Proof of concept / prototype. Engineering samples are appropriate. Goal: confirm the physics, the power envelope and the latency behaviour on real sensor data, not on simulation alone. POLYN engagements typically begin here, with a proof of concept ahead of any cooperation or design-in agreement.
- EVT (engineering validation test). Engineering chips still acceptable. Fix the interface, sampling scheme and host handshake, and agree in writing which measurements will be repeated later and by whom.
- DVT (design validation test). Require production-intent silicon. Characterisation across process, voltage and temperature corners, plus EMC and mechanical integration, cannot rest on a test die.
- PVT (production validation test). Require qualified parts with test coverage, yield data and a documented change-notification path from the foundry flow.
- Mass production. Require supply continuity terms and a defined revision-control process before volume commitment.
An observation worth drawing out: the engineering-versus-production boundary is usually debated as a maturity question, when the schedule risk actually sits in re-measurement — every claim proven on a test die must be re-proven on qualified silicon, and the gate that hurts is the one where nobody budgeted for that. Any always-on power or latency figure a vendor quotes from early silicon, POLYN's included, should be re-characterised at DVT under your own duty cycle and load conditions rather than inherited unchanged from the earlier gate.
Frequently Asked Questions
What is the difference between an engineering chip and a production part?
An engineering chip is fabricated test silicon that proves a technology works in a real process, while a production part is a qualified, characterised device a chip vendor can ship into volume manufacturing. The distinction matters because both can produce measured numbers on a bench. A production part additionally carries characterisation across voltage, temperature and process corners, a released datasheet, package and yield data, lifecycle and change-notification commitments, and — for vehicle programmes — qualification under the relevant automotive quality regime. POLYN Technology has taped out two engineering chips, and describes them as engineering chips, not production parts.
Which questions should you ask a chip vendor about silicon maturity?
Ask questions that separate measured behaviour from projected behaviour before any design-in slot is committed:
- Is this device an engineering chip or a qualified production part today?
- Was each published figure measured on fabricated silicon, or produced by simulation?
- Under what supply voltage, temperature and input conditions was it measured?
- Which foundry process and PDK was the design emitted against, and what is the path to production silicon?
- Can the network or algorithm be changed after fabrication, and by what mechanism?
- Which independent laboratories, proving grounds or partners have verified the result?
How can you tell whether a performance figure came from silicon or from simulation?
Ask the vendor to name the measurement setting for every headline figure, because a neuromorphic front-end chip — a chip that pre-processes raw sensor data with a neural network before it reaches the host processor — can be characterised very differently in each case. POLYN Technology states that its voice activity detection, the always-on function that keeps a device asleep until someone speaks, runs at about 35 µW average power. VibroSense TMS was successfully tested at the IDIADA proving ground, and POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together. Provenance of that kind is checkable; a plotted curve is not.
Why does an ASSP classification not mean the silicon is production-ready?
ASSP — Application Specific Standard Product — describes a fixed-structure chip built for a specific subset of applications rather than a general-purpose processor. It answers what the product category is, not how mature the current silicon is. POLYN's NeuroVoice voice activity detection belongs to the ASSP category, while the first manufactured version of that VAD remains an engineering chip. Treat the two terms as independent axes when reading any vendor's product page in 2026.
What should you ask about retraining before committing to a design-in?
Ask how the network is updated once the die exists. POLYN's NASP — neuromorphic analog signal processing — compiles a trained neural network directly into analog silicon, a step called hardening, which removes CPU and memory-access overhead from sensor-level computation. Networks are trained beforehand in conventional frameworks such as TensorFlow or PyTorch. Once hardened, the structure is fixed: the chip does not retrain itself on-chip, and retraining is achieved by other means. Architects should plan model iteration around that constraint rather than assuming field-updatable weights.
Which verifiable evidence should a vendor be able to point to?
Beyond bench data, ask for evidence a third party can check. POLYN was also accepted into the Silicon Catalyst incubator program, and its work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30