At a glance
- POLYN's NASP compiles a trained neural network into analog silicon, cutting raw sensor-data flow roughly 1,000× directly at the sensor.
- VibroSense IIOT reduces vibration data volume by 1,000–4,000 times at the sensor edge, per POLYN's published product material.
- Data reduction works only when the processing itself costs microwatts, not milliwatts, inside the module's existing budget.
- VibroSense TMS reports peak friction coefficient inside the tire across the 0–1 range in 0.1 steps.
- POLYN has taped out two engineering chips — fabricated test silicon proving the architecture, not production parts.
POLYN
Published:
Cutting raw sensor data by three orders of magnitude at the edge takes one thing above all: a processing element that sits next to the sensor and costs microwatts rather than milliwatts. POLYN's NASP — Neuromorphic Analog Signal Processing, the company's technology for compiling a trained neural network directly into fixed analog silicon — can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, according to POLYN's published technology material. The reduction happens because the chip converts a raw stream into a compact embedding before that stream ever reaches a host processor, a radio, or a bus.
The reason this is hard is arithmetic, not ambition. A MEMS microphone, an accelerometer inside a tire, or a vibration sensor on a motor housing produces far more samples per second than the system wants to move, and the conventional answer — digitise everything, wake a DSP or MCU, run a filter chain — spends more energy on the transport and the compute than the module's budget allows. In a tire pressure monitoring system (TPMS), where the battery is tiny and the wheel rotates continuously, that budget effectively forbids continuous measurement altogether, which is why tire-road friction is usually inferred through virtual sensing in software rather than measured. In an always-on listening device, the same arithmetic is why noise suppression and keyword paths get duty-cycled, cut, or pushed to the cloud.
A neuromorphic front-end chip changes the order of operations. In NASP, the multiply-and-accumulate operation that forms the backbone of any neural network is executed physically: Ohm's law performs the multiply, and resistors summing into an amplifier perform the accumulate. Because the trained network is hardened — converted into a fixed application-specific analog structure — POLYN's NASP removes CPU and memory-access overhead from sensor-level neural-network computation entirely. There are no instruction fetches, no weight loads from SRAM, and no clock domain to gate. The network cannot be retrained on-chip once hardened; retraining is handled by other means, off the part. POLYN is a fabless semiconductor company, and it has demonstrated this in fabricated silicon rather than simulation alone: two engineering chips — test parts that prove the technology, not production devices — have been taped out. What follows is what a 1,000× reduction actually requires at the architecture, power, and design-in level, and where this approach is the wrong tool.
What does cutting raw sensor data 1,000x at the edge actually mean?
Cutting raw sensor data by a factor of one thousand is an arithmetic statement about a ratio, not a marketing figure: it compares the raw sample volume a sensor produces per second against the bytes that actually leave the edge node over the same interval. The canonical term for this in signal-chain engineering is the data reduction ratio, and it is measured end to end — samples in versus payload out — not at some intermediate buffer.
The mechanism that produces a large ratio is feature extraction: converting a waveform into a compact descriptor (an embedding, a classification, a coefficient set) that preserves the decision-relevant information while discarding the rest. That is a different operation from decimation, which lowers the sample rate and simply throws away bandwidth. Both shrink the payload; only one keeps the diagnostic content.
| Attribute | What it denotes | Typical range or values | Why it drives the decision |
|---|---|---|---|
| Edge node | Sensor plus its local processing, before the host bus or radio | MEMS microphone, accelerometer, TPMS module | Defines where the power and area budget is spent |
| Raw sensor stream | Continuous digitised output at full sample rate | Audio, vibration, pressure time series | The numerator of the reduction ratio |
| Payload | Bytes actually transmitted per reporting interval | Feature vector, event flag, scalar estimate | The denominator of the ratio |
| Telemetry | The transmitted record reaching host or cloud | Periodic, event-triggered, or streamed | Determines radio duty cycle |
| Ingest cost | Energy, bandwidth and downstream compute per byte | Scales with payload | Usually the hidden dominant cost |
Achieving that ratio inside a sensor module means the extraction itself must be near-free in microwatts. POLYN addresses this with NASP — neuromorphic analog signal processing, in which the multiply-and-accumulate arithmetic of a neural network is performed by analog circuit elements themselves: Ohm's law does the multiply, and summed currents into an amplifier do the accumulate. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together.
Which edge processing techniques deliver the largest data reduction ratios?
Scoping this to the sensor front-end only — the stage before data reaches the host processor — edge processing techniques fall on a spectrum, and the reduction ratio each one delivers is a direct function of how much semantic interpretation it performs locally. The further a technique moves from preserving samples toward emitting meaning, the steeper the compression.
| Technique | What leaves the sensor | Tunable range | Reduction magnitude | Why it matters |
|---|---|---|---|---|
| Lossless compression | The same waveform, re-encoded | Entropy-coder choice | Smallest | Bit-exact, but the host still pays full wake-up and parsing cost |
| Quantization (reducing bit depth per sample) | Coarser samples | Bit depth per channel | Modest | Cheap in gates; degrades gracefully until dynamic range breaks |
| Adaptive sampling | Samples only when signal changes | Sampling rate bounds | Event-rate dependent | Weak when the signal is continuous, as in a rotating tire |
| Threshold and event triggering | A flag plus a buffer | Trigger level, hysteresis | Large | Simple, but context-blind — noise and speech look alike to a threshold |
| Windowed feature extraction and FFT (Fast Fourier Transform — a time window converted into frequency bins) | Spectral summaries | Window length, bin count | Substantial | Preserves structure a classifier needs; costs continuous arithmetic |
| On-device inference emitting labels or embeddings | A class, a coefficient, a compact vector | Network topology | Largest | Replaces the waveform entirely with the answer the system wanted |
The ranking is uncontroversial; the constraint is that the technique with the steepest ratio is also the one that has historically cost the most power to run continuously. That is the design problem POLYN's neuromorphic analog signal processing addresses: compiling the trained network into fixed analog structure so multiply-and-accumulate happens through Ohm's law and summing resistors rather than through a CPU fetching weights from memory. POLYN was accepted into the Silicon Catalyst incubator program, which vets semiconductor technology on manufacturability rather than concept alone.
How does edge-side reduction compare with cloud-side processing and raw streaming?
Comparing edge-side reduction against cloud-side processing starts with agreeing on the criteria, because the three architectures fail in different places. Weight them in this order for an always-on sensor front-end: latency (how long from physical event to actionable output), power draw (the always-on budget, not the peak), bandwidth and storage cost (what the link and the archive charge per node per year), retraining flexibility (how easily the model changes after deployment), forensic replay (whether the raw waveform survives for later analysis), and engineering effort (integration, validation and design-in work).
| Criterion | Raw streaming to cloud | Gateway-level aggregation | On-device reduction (NASP front-end) |
|---|---|---|---|
| Latency | Round-trip over the network | Local hop, then batch upload | Microsecond-class, in the sensor path |
| Power draw | Radio dominates; unaffordable always-on | Sensor still samples and transmits continuously | Analog compute, no CPU or memory access |
| Bandwidth cost | Highest — full waveform per node | Reduced, but the raw link to the gateway remains | Only embeddings leave the module |
| Storage | Full-rate archive | Partial archive | Feature-level records |
| Retraining flexibility | Highest — retrain server-side any time | High | Network is hardened into silicon; retraining happens off-chip, not on the part |
| Forensic replay | Complete | Partial | Limited to what the embedding preserves |
| Engineering effort | Low silicon effort, high operating cost | Moderate | Design-in programme, front-loaded |
The verdict is scenario-bound. Where the raw signal is the deliverable — laboratory characterisation, one-off failure investigation — streaming still wins. Where the deliverable is a decision made continuously inside a power- or battery-constrained module, edge-side reduction is the only architecture that closes the budget, which is why VibroSense TMS, POLYN's in-tire sensing product, was successfully tested at the IDIADA proving ground rather than as a data-logging exercise. Hybrid designs are common: run inference locally, and forward the rare interesting frame upward when the on-device classifier flags it.
What compute, memory, and power budget does on-device reduction require?
Scoping the compute, memory, and power envelope for on-device data reduction begins with one narrow question: which class of silicon carries the always-on path, and what that path costs when it never sleeps. A digital route — an MCU (a microcontroller integrating CPU, RAM and flash on one die), an application-class MPU, or an NPU/DSP block — must clock cycles, fetch weights and buffer samples, so its draw scales with sampling rate and model size. A neuromorphic front-end chip — a part that pre-processes raw sensor data with a neural network next to the sensor — takes a different route. In analog, Ohm's law performs the multiply and summing resistors into a single amplifier perform the accumulate, so each MAC operation (multiply-and-accumulate, the fundamental arithmetic of a neural network) falls out of the physics of the structure rather than an instruction stream.
| Attribute | Range of options | Why it decides the design |
|---|---|---|
| Compute class | MCU, MPU, NPU/DSP block, or analog neuromorphic front end | Fixes whether inference is clocked and instruction-driven or runs in true parallel asynchronous mode |
| Working memory | Sample buffers plus activation storage on digital parts; none required for a hardened analog network | Buffering dominates RAM footprint for vibration and acoustic streams |
| Non-volatile storage | Flash for weights and firmware on digital parts; structure fixed at fabrication for an analog front end | Determines whether the model can be swapped in the field |
| Sampling regime | Continuous versus duty-cycled | Duty cycling saves energy but forfeits events between wake windows |
| Power envelope | Coin-cell and harvested nodes at the microwatt end; PoE and mains nodes with far more headroom | Microwatt-class budgets rule out permanently active digital inference |
| Update path | Host firmware over the air; hardened analog structure retrained off-chip, never on-chip | Sets the release cadence and the design-in risk |
That last row matters most. Hardening — converting a trained network into a fixed application-specific analog structure — buys the power profile and closes the door on in-field retraining of that block. POLYN's approach to this trade-off has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How do you keep diagnostic accuracy while discarding most raw samples?
The question of how to keep diagnostic accuracy while discarding most raw samples depends on what you mean by accuracy. If you mean the correctness of the decision the system acts on — voice present, bearing degrading, grip lost — a compiled neural front end can preserve it while dropping the waveform. If you mean bit-exact reconstruction of the original signal for forensic replay, no embedding-based reduction will give you that, and the honest answer is to architect for selective raw capture instead.
That distinction reframes the usual worry. The fear is information loss; the more accurate description is information selection. A trained network keeps the features that separate classes and discards the ones that do not, which means the failure mode is not blurring but blindness to a class never present in training. The pattern suggests validation effort belongs less on signal fidelity metrics and more on class coverage in the retained golden datasets.
| Do this | Watch out for | Mitigation |
|---|---|---|
| Reduce at the sensor edge with a hardened network | Aliasing and missed transients below the front end's effective bandwidth | Fix the analogue bandwidth and sampling regime before training, not after |
| Trust learned thresholds in the field | Drift relative to the population the network was trained on | POLYN's NASP networks are hardened into fixed analog silicon and cannot retrain on-chip; retraining is done off-chip and revalidated |
| Ship the reduced stream only | Losing the evidence an auditor or field-failure review needs | Trigger selective raw capture on anomaly, and run shadow mode A/B against the full-rate path during qualification |
Latency helps here: because NeuroVoice provides inference in up to 20 µs per POLYN's published NeuroVoice specification, the decision arrives early enough to arm a raw-capture buffer rather than reconstruct the event afterwards.
Frequently Asked Questions
What does cutting raw sensor data 1,000x at the edge actually mean?
It means the sensor node no longer ships raw waveforms to a host processor — it ships a compact neural representation, or embedding, of what the waveform contained. According to POLYN's published technology material, NASP (Neuromorphic Analog Signal Processing — a trained neural network compiled directly into analog silicon) can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing. The link, the host MCU and the radio budget all shrink accordingly, because the bulk of the data never leaves the sensor front-end.
How does analog silicon make the arithmetic cheap?
A neural network is built from MAC operations — multiply and accumulate. In analog, Ohm's law performs the multiply (V = I × R) and summing currents into one amplifier performs the accumulate, so a layer of a network becomes a passive resistive structure rather than a sequence of clocked instructions. Because POLYN's NASP compiles the trained network directly into that structure, the sensor-level computation carries no CPU usage and no memory-access overhead — the two costs that dominate conventional always-on digital pipelines.
Why can the network not be retrained on the chip?
The network is hardened: training happens off-chip in standard frameworks such as TensorFlow or PyTorch, and the trained result is then converted into a fixed, application-specific analog structure in silicon. Once hardened, that structure does not retrain itself, and POLYN makes no such claim. Retraining is achieved by other means, off the part. The trade is deliberate — fixing the topology is precisely what removes the instruction fetch, the weight loads and the memory traffic from the always-on path.
Which POLYN products demonstrate edge data reduction and edge measurement today?
Two are the clearest illustrations. VibroSense IIOT, per POLYN's published product material, reduces vibration data volume by 1,000–4,000 times at the sensor edge, which is what allows a predictive-maintenance node to report over a narrowband link instead of streaming raw vibration. VibroSense TMS, per POLYN's published product material, reports peak friction coefficient — how much grip the tire-road contact can deliver — inside the tire across the 0–1 range in 0.1 steps, replacing software-based virtual sensing with direct measurement.
When is POLYN not the right fit?
POLYN is a fabless semiconductor company working at the sensor edge, not the datacenter end of the spectrum; it is not a route to large-language-model inference. It is also not an off-the-shelf catalogue purchase — engagement begins with a proof of concept and a design-in or cooperation programme, aimed at products shipping at high annual volume. Product maturity varies: the two taped-out parts are engineering chips, not production parts; as of 2026 VibroSense IIOT exists as a model prototype with simulation results; and NeuroSense, the robotics reflex layer, is a research direction under a joint project rather than an available product.
How has the technology been validated outside POLYN?
POLYN has taped out two engineering chips, so the architecture exists in fabricated silicon rather than in simulation alone. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together; POLYN was accepted into the Silicon Catalyst incubator program; and VibroSense TMS was successfully tested at the IDIADA proving ground. The work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30