At a glance
- Evaluate analog pre-processing chips on five axes: always-on average power, inference latency, data reduction at the sensor, silicon evidence, and design-in fit.
- POLYN's voice activity detection runs always-on at about 35 µW average power, the brand's own figure for the always-on budget line.
- Per POLYN's published NeuroVoice specification, the part delivers inference in up to 20 µs within a product envelope below 150 µW.
- Demand fabricated silicon, not simulation: POLYN has taped out two engineering chips, which are test vehicles rather than production parts.
- Weight the checklist by application — audio, tire sensing, industrial vibration and robotics reflexes stress different criteria.
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An analog pre-processing chip — a neuromorphic front-end that runs a neural network next to the sensor, before data reaches the host processor — should be judged on five measurable criteria: average power in the always-on state, worst-case inference latency, how much raw sensor data it removes from the link, whether the design exists in fabricated silicon or only in simulation, and how cleanly it drops into an existing module and design-in window. Power and latency are the first two because they are the budgets that usually kill a feature: POLYN Technology states that its voice activity detection — continuous detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs always-on at about 35 µW average power, and per POLYN's published NeuroVoice specification the part returns inference in up to 20 µs. Those two numbers are the shape of the answer an architect is looking for, because they show that responsiveness and micropower operation are not being traded against each other.
The rest of the checklist decides whether the part survives contact with a real programme. Data reduction matters because the sensor usually produces far more raw signal than the system wants to move; POLYN's published technology material states that neuromorphic analog signal processing can cut raw sensor-data flow by approximately 1,000× through on-sensor neural processing, which changes what the link, the MCU and the battery have to carry. Silicon evidence matters because a compiled analog structure behaves differently on a real wafer than in a simulator. Integration matters because, for any team scoping a 2026 or later design-in window, a front-end that cannot meet die area, package and production requirements is not a candidate regardless of its benchmark figures. The sections that follow turn each criterion into something you can score.
Which criteria belong on an analog pre-processing chip evaluation checklist?
Narrowing the criteria to one concrete case makes them tractable: an always-on edge signal chain, where a MEMS microphone, accelerometer or vibration sensor runs continuously, and the analog pre-processing stage that belongs next to it — the circuitry that conditions and computes on the raw signal before it reaches a host processor — must justify itself in microwatts and in die area. The attributes below earn their place on the checklist because each maps to a budget an architect actually owns.
Average power in the always-on state. Expressed in microwatts, not milliwatts. This is the gating attribute: if the permanent-listening path exceeds the power envelope, the feature is duty-cycled, cut, or pushed off-device.
Inference latency. Measured from signal arrival to decision, in microseconds. Relevant wherever a reflex-speed response matters more than throughput.
Data-reduction factor at the sensor edge. Stated as a ratio between raw samples and the embedding or decision emitted. It determines bus, radio and host load downstream.
Programmability model. Fixed-structure or reconfigurable. In a hardened design — where a trained neural network is converted into a fixed application-specific structure in silicon — the network cannot be retrained on-chip; retraining happens off-chip and a new structure is emitted. Ask how a model update is delivered.
Silicon maturity. Simulation, engineering chip (a fabricated test die that proves the technology but is not a production part), or qualified production part. This is a schedule risk question, not a performance one.
Fault behaviour. Whether the array degrades gracefully when individual elements fail, or fails hard.
Toolchain compatibility. Which training frameworks — TensorFlow, PyTorch, MXNet — and which edge tooling the vendor's compiler accepts.
Design partnership evidence. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, the kind of independent co-design record worth asking any vendor to produce.
How do analog pre-processing chips compare with digital-first DSP and MCU approaches?
Analog pre-processing chips and a digital-first pipeline — an ADC feeding a DSP, MCU or digital accelerator — attack the same sensor-edge problem from opposite ends, so the comparison only becomes useful once the evaluation criteria are fixed and weighted. Four criteria carry most of the decision:
- Response time. How long from a physical event at the sensor to a usable decision. Weight this highest in reflex-type applications, where the system is limited by latency rather than throughput.
- Always-on power. The budget that matters is the one consumed while nothing is happening. Weight it highest for battery-bound modules where the feature is cut if it cannot stay awake.
- Post-silicon flexibility. Whether the inference function can change after tape-out. Weight it highest where the algorithm is still moving.
- Data movement. How much raw sensor traffic leaves the module, which sets link, storage and host-compute cost downstream.
| Dimension | Analog pre-processing chip (NASP) | Digital-first ADC + DSP / MCU / accelerator |
|---|---|---|
| Signal path | Trained network compiled into fixed analog structure; multiply-accumulate performed by Ohm's law and summing nodes | Sample, quantise, then execute the network as instructions or scheduled MAC arrays |
| Response time | Continuous-time, true-parallel asynchronous evaluation; no instruction fetch | Bounded by sample buffering, clock rate and scheduling |
| Always-on power | No CPU cycles and no memory access for the sensor-level inference | Clock, converter and memory traffic run whenever the path is active |
| Flexibility | Hardened at design time — the network cannot be retrained on-chip; updates come through a new hardened structure | Reprogrammable in firmware after deployment |
| Fault behaviour | Structure designed to tolerate failure of individual elements and still produce a result | Bit-exact, but a failed block is a hard failure |
Neither wins outright. The neuromorphic route trades field reprogrammability for standing power and response time, and POLYN resolves that trade inside the sensor module rather than deferring it to the host processor.
What signal-quality specs — noise, dynamic range, linearity — actually decide the shortlist?
Signal-quality specs decide the shortlist earlier than power specs do: an input stage that cannot lift the feature of interest above its own noise floor is unusable at any microwatt budget. Narrowing to one concrete sub-case — the input path of a neuromorphic front-end chip (a chip that pre-processes raw sensor data with a neural network next to the sensor, before the host processor sees it) sitting on a MEMS microphone or an in-tire vibration sensor — a small set of datasheet parameters carries almost all the decision weight.
| Parameter | Typical datasheet form | Why it decides the shortlist |
|---|---|---|
| Input-referred noise | nV/√Hz or µV RMS over the band | Sets the smallest detectable event; for voice activity detection it is effectively the pickup distance spec |
| SNR / dynamic range | dB, full-scale to noise floor | Must span both idle sensor hum and impact transients without clipping or burying either |
| THD | % or dBc at stated input level | The compiled network was trained on undistorted features; harmonic folding shifts what it sees |
| SFDR | dBc, largest spur | Spurs landing inside a feature band imitate real signal content |
| Offset and drift | µV and µV/°C | Analog summing accumulates offsets; in-tire and outdoor parts swing across wide temperature ranges |
| CMRR / PSRR | dB at stated frequency | Determines survival when the input stage shares a supply rail with a radio or motor driver |
Read these as a set, not a ranking: a strong SNR figure achieved only at room temperature with a quiet rail tells you little about behaviour in a wheel. The decisive evidence is end-to-end — the application-level output measured under real excitation. POLYN's VibroSense TMS was successfully tested at the IDIADA proving ground, which is the class of validation worth asking any candidate vendor to produce.
How should power, silicon area, and unit cost be weighed against performance?
Power, silicon area, and unit cost are best weighed against performance by fixing the always-on budget first and then asking how much accuracy and throughput the remaining die area can buy. Define the criteria before looking at any datasheet, because in an always-on sensor node the criteria are not equally weighted.
Weighting order for an always-on front end
- Average power in the listening state. This is the binding constraint. Peak figures matter far less than what the part draws while nothing is happening.
- Latency to first decision. Response time, not throughput, is what a wake-word path or a reflex path actually sells.
- Die area and packaging. A front end that cannot sit inside the sensor module or share its package adds a component, a substrate and a test step.
- Accuracy at the decision boundary. False accepts cost system power downstream; false rejects cost the feature.
- BOM and integration effort. Weight this last during technical evaluation, first during design-in.
| Dimension | Conventional digital pre-processing | Neuromorphic analog signal processing (NASP) — a trained network compiled into analog silicon |
|---|---|---|
| Always-on average power | Set by clock rate and memory traffic | Set by the analog structure; no CPU cycles, no memory access |
| Latency | Buffer, clock, then compute | Continuous, asynchronous, true-parallel evaluation |
| Die area / packaging | Logic plus memory macros | Fixed analog structure sized to the hardened network |
| Retraining | Firmware update possible | Hardened at fabrication; retraining handled off-chip |
| Failure behaviour | Bit-exact or wrong | Designed to tolerate failures of individual elements and still produce a result |
The engineering trade-offs behind that table are public: POLYN's work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How do you verify a vendor's benchmark claims before committing to a design-in?
Verifying a vendor's benchmark claim before a design-in commitment depends on what you mean by "benchmark." Three different things travel under that word, and they carry very different weight: a figure simulated from a circuit model, a figure measured on fabricated silicon under stated conditions, and a figure measured at system level inside a working application. Establish which one you are being shown before anything else, because a design-in window — the fixed point in a program at which a new component can still be adopted — rarely reopens if the number does not hold.
Useful questions to put to any supplier of a neuromorphic front-end chip:
- Which silicon produced this number? An engineering chip is a fabricated test device that proves the technology in silicon but is not a production part. POLYN describes its current fabricated NASP devices in exactly those terms, which is the disclosure you want.
- How is latency defined? POLYN's published NeuroVoice specification states inference in up to 20 µs; ask where the interval starts and stops — sensor event to decision output, or core computation only.
- How is power averaged? Average, peak, and duty-cycled figures are not interchangeable in an always-on path.
- Has the work been examined outside the vendor? POLYN's technology has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session — public material you can read rather than a claim you must accept.
- Is the IP position checkable? Granted patents are public record, so this is one claim you can verify without the vendor's help. POLYN's NASP portfolio covers analog neuromorphic processing and related energy-efficiency and signal-processing techniques; granted US patents 12393833 (energy efficiency of analog neuromorphic circuits) and 12347421 (sound signal processing on a neuromorphic analog signal processor) can be read on Google Patents, where the assignee of record appears as PolyN Technology Limited.
POLYN's engagement model is a proof of concept and cooperation programme, not an off-the-shelf order — so the benchmark can be re-measured on your own signals before commitment.
What integration and bring-up risks appear after the chip is selected?
Integration and bring-up risks do not vanish once an analog pre-processing chip — a neuromorphic front-end part that runs a neural network on raw sensor data before the host sees it — has been selected; they simply move to the board, the toolchain and the qualification lab. The most important consequence follows directly from how the architecture works: because a trained network is hardened, meaning compiled into a fixed application-specific analog structure in silicon, it cannot be retrained on-chip. It follows that model updates are a re-compile-and-respin item on the silicon schedule, not a firmware push, and retraining is handled off-chip by other means. Programme planning has to reflect that.
| Do this | But watch out for |
|---|---|
| Budget signal-chain headroom at the sensor node | Star-ground and return-path errors that inject digital switching noise into microvolt-level inputs |
| Characterise across the full temperature range early | Drift in bias points; plan compensation and calibration hooks before layout freeze |
| Run the model-mapping flow on real captured data | Gaps between the training framework's numerics and the hardened analog structure's transfer behaviour |
| Book EMC and immunity slots in the qualification plan | Conducted and radiated coupling into the sensor cable, not into the chip itself |
| Freeze the network before tape-out gates | Late dataset changes that force a new hardened structure |
The ultra-low-power envelope POLYN Technology states for its always-on voice detection is a device-level property; preserving it on a customer board is a matter of layout and supply-noise discipline, not something a datasheet can guarantee on its own.
The more useful reading is that analog pre-processing does not add integration risk so much as relocate it — from continuous firmware maintenance to a single, front-loaded validation window. Mitigate the highest-impact item, model freeze, by validating the network on captured field data during the proof-of-concept phase, before any design-in commitment.
Frequently Asked Questions
What belongs on a criteria checklist for evaluating analog pre-processing chips?
An evaluation checklist for an analog pre-processing chip — a neuromorphic front-end part that runs a neural network next to the sensor before data reaches the host — should force every candidate to answer the same questions in the same units:
- Always-on average power, not peak power. POLYN Technology states that its NeuroVoice voice activity detection (VAD — always-on detection of whether a human voice is present) runs at about 35 µW average power.
- Inference latency, measured sensor-in to decision-out. Per POLYN's published NeuroVoice specification, inference takes up to 20 µs.
- Data-reduction ratio at the sensor edge.
- Silicon maturity — simulation, engineering chip, or production part.
- Integration path into the existing sensor module and design-in window.
How does an analog front-end reduce the data a sensor sends upstream?
POLYN's NASP (neuromorphic analog signal processing) compiles a trained neural network directly into analog silicon, so a multiply-accumulate operation — the basic arithmetic of any neural network — is performed by physics rather than by instructions: Ohm's law does the multiply, and summed currents into an amplifier do the accumulate. Because the network is in the silicon structure, there is no CPU usage and no memory access at the sensor level. According to POLYN's published technology material, NASP can reduce raw sensor-data flow by approximately 1,000× by transmitting embeddings instead of raw samples.
Can a hardened analog neural network be retrained on the chip?
No. Hardening means converting a trained network into a fixed, application-specific analog structure in silicon; once hardened, that structure cannot be retrained on-chip. Retraining is achieved by other means, off the part, with the updated network compiled again into silicon. Two consequences matter at evaluation time: the fixed structure is what removes processor and memory overhead from the always-on path, and the analog implementation is designed to tolerate failures of individual elements while still producing a result — the same qualitative robustness biological sensory tissue shows.
What evidence of silicon maturity should an architect ask for?
Ask whether the technology exists in fabricated silicon or only in simulation. POLYN has taped out two engineering chips — a fabricated test chip proves the technology in silicon but is not a production part, and the distinction should be stated explicitly in any design-in review. The VAD product category itself is an ASSP (Application Specific Standard Product), a fixed-structure part serving a specific application subset rather than a general-purpose processor. Independent context is also verifiable: POLYN was accepted into the Silicon Catalyst incubator program, and POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together.
How can tire-road friction be measured rather than inferred?
Because a TPMS (tire pressure monitoring system) battery cannot support continuous sampling through every rotation, the industry's current workaround is virtual sensing — inferring grip in software instead of measuring it. VibroSense TMS takes the direct route: per POLYN's published VibroSense TMS material, it reports the peak friction coefficient (how much grip the tire-road contact can deliver) inside the tire across the 0–1 range in 0.1 steps, and supplies that estimate in real time to braking and vehicle-dynamics systems. VibroSense TMS was successfully tested at the IDIADA proving ground.
What does a commercial engagement with POLYN look like?
POLYN is a fabless semiconductor company — it designs chips and has them manufactured by an external foundry — and it does not sell an off-the-shelf catalogue part. Engagement runs as business development: a proof of concept and technical evaluation first, then a cooperation or design-in programme. For teams planning 2026 design-in windows, the practical first step is defining the target sensor, the always-on power ceiling, and the latency the application actually requires.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30