At a glance
- Compiling a trained network into analog silicon means hardening fixed weights into circuits, so verification replaces retraining as the main risk control.
- Verify transfer accuracy, process and temperature variation tolerance, latency under load, and power at the operating point, not just at datasheet peak.
- NASP compiles a trained network directly into analog silicon, removing CPU cycles and memory access from sensor-level inference.
- NeuroVoice operates within an ultra-low-power product envelope below 150 µW, per POLYN Technology's published NeuroVoice materials.
- POLYN Technology has taped out two engineering chips — silicon evidence, not simulation — with partners including Fraunhofer Mikroelektronik.
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Compiling a trained network into analog silicon is the process of converting a neural network trained in a standard framework — TensorFlow, PyTorch or MXNet — into a fixed, application-specific analog circuit, where each weight becomes a physical component value rather than a number fetched from memory. Because the resulting structure is hardened — permanently fixed at fabrication, with no on-chip retraining path — every property that matters has to be confirmed before tape-out rather than patched afterwards. The items an architect must verify are, in order: transfer accuracy from the trained model to the fabricated circuit, tolerance to process, voltage and temperature variation, inference latency measured end to end at the sensor, average power at the real duty cycle rather than at a peak-performance operating point, and graceful behaviour when individual analog elements drift or fail.
That list matters because analog inference trades a familiar failure mode for an unfamiliar one. In a digital pipeline, a multiply-accumulate operation — the multiply-and-add arithmetic at the heart of every neural layer — returns a bit-exact result, and the cost shows up as clock cycles, memory bandwidth and milliwatts. In analog, Ohm's law performs the multiply and a summing node performs the accumulate, so the computation is effectively free in cycles but inherits the tolerances of real components. The verification question is therefore not "is the arithmetic exact?" but "does the compiled network still make the same decision across the corners of the process and the temperature range the product ships into?" Answering that requires silicon, not simulation alone — one reason POLYN Technology has taped out two engineering chips of its neuromorphic analog signal processing (NASP) architecture, which compiles a trained network directly into analog silicon and removes CPU usage and memory access from sensor-level neural computation.
What exactly gets verified when a trained network is compiled into analog silicon?
The scope here is narrow, and it helps to say exactly what gets verified: not the model's accuracy inside a training framework such as TensorFlow or PyTorch, but the fidelity of the mapping once that trained network is hardened — converted into a fixed application-specific analog structure in silicon, after which it cannot be retrained on-chip. Retraining happens off-chip, so every property below has to be checked before tape-out.
The artifacts and attributes worth checking
| Attribute | Range or form it takes | Why it matters |
|---|---|---|
| Weight-to-conductance mapping | Target conductance or resistance per synapse, bounded by device sizing rules in the foundry PDK | A MAC operation — multiply and accumulate — is realised by Ohm's law and summed currents, so weight error becomes physical mismatch |
| Signal headroom | Input voltage swing at the analog front-end, referenced to the supply rails | Clipping at a layer boundary silently distorts downstream activations |
| Converter boundaries | DAC and ADC resolution and sample rate where the analog domain meets the digital host | Sets the true quantisation floor of the chain, not the nominal weight precision |
| Element mismatch | Process, voltage and temperature corners, plus Monte Carlo spread across the array | Shows whether accuracy holds across a production distribution, not just a typical die |
| Latency path | Settling time through the parallel asynchronous network, with no clocked memory access | This is where the response-time advantage is either real or lost |
What closes the loop
Simulation alone settles none of these; correlation between simulated behaviour and measured silicon does. Design partnerships matter for the same reason — POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and co-design arrangements of that kind bring outside engineering eyes to a programme.
Why do device non-idealities and programming error make bit-exact verification impossible?
Device non-idealities and conductance programming error break the assumption that underpins digital sign-off — that two representations of one design can be proven identical. In an analog compiled network, no such proof exists, because the silicon does not replay the same arithmetic twice.
This depends on what you mean by "verification". Two readings are in circulation, and they lead to different sign-off plans.
Reading one: equivalence checking. In digital flows, formal logical equivalence checking (LEC) proves that a gate-level netlist implements the same Boolean function as its RTL source. A digital multiply-accumulate array produces the same bits on every run, so a mismatch is a bug. Applied to analog compute, this reading does not carry over: the multiply is Ohm's law and the accumulate is summed current, both continuous quantities with no golden bit pattern to compare against.
Reading two: statistical accuracy bounding. Here the reference is the trained network in floating point, and the question is how far the fabricated part's output distribution drifts from it across process corners, supply, temperature and time. The sources of that drift are enumerable:
| Error source | Mechanism | Verification consequence |
|---|---|---|
| Conductance programming error | Static offset between target and realised weight | Weight-perturbation Monte Carlo |
| Cycle-to-cycle noise | Thermal and flicker noise on each run | Repeat-trial spread, not single-run pass |
| IR drop | Supply gradient across the array | Position-dependent gain checks |
| ADC quantization | Finite output resolution | Sets the error floor |
| Nonlinearity | Departure from ideal transfer at large swing | Signal-swing-limited operating range |
The second reading is the operative one. Sign-off shifts from equality to a bounded task-level metric — detection rate, classification accuracy, coefficient error — held across corners. POLYN was accepted into the Silicon Catalyst incubator program, a semiconductor-focused incubator outside the company.
Which verification stages should a compile-to-analog pipeline include, and in what order?
When you are evaluating a compile-to-analog flow at design-in, the verification stages matter less as a checklist than as an ordering: each stage must close a class of risk that the next one cannot detect. This is written for the technical-evaluation stage of the buying journey — after the concept is credible, before any commitment to a design-in window.
- Graph lowering checks. Lowering is the translation of a trained checkpoint (from PyTorch, TensorFlow or MXNet) into primitives the analog fabric can physically realise. Verify that every operator maps to an implementable structure — the multiply-accumulate, or MAC, becomes Ohm's law across a resistor and a summing node at an amplifier — and that weight range, fan-in and signal swing stay inside the fabric's limits. Unsupported operators must fail loudly here, not later.
- Hardware-aware simulation. Re-run the task with device-level effects applied: thermal and flicker noise, amplifier offset, resistor mismatch, temperature drift and process corners. The metric is task accuracy against the trained baseline, not signal-to-noise ratio in isolation.
- Tile-level emulation. Compare a fabricated building block's measured transfer function against its simulated one. Systematic modelling error is caught here, before it is replicated across the full array.
- Silicon bring-up. Exercise the engineering chip — a fabricated test die that proves the technology in silicon but is not a production part — against golden input vectors, then sweep supply and temperature.
- System and field validation. Move to the real signal environment. POLYN's VibroSense TMS, for instance, was successfully tested at the IDIADA proving ground rather than in simulation alone.
- Field monitoring. Because the network is hardened into fixed structure, drift is tracked in the field and corrections are trained off-chip, then re-hardened — never on the die.
How does analog compilation sign-off compare with digital accelerator verification?
Analog compilation sign-off and digital accelerator verification answer the same question — does the silicon reproduce the trained network? — but they rest on different evidence, so fix the evaluation criteria before comparing. Determinism carries the most weight: a digital neural processing unit (NPU) executes quantised arithmetic that a bit-accurate reference model reproduces exactly, whereas an analog structure returns a distribution shaped by process, voltage and temperature (PVT) variation. Coverage metric follows from that, since counting exercised operators is meaningful only when execution is repeatable. Tolerance definition — the allowed deviation between silicon and the trained model — is implicit in digital flows and must be stated explicitly in analog ones. Regression strategy is weighted last but drives schedule risk, because analog re-verification is tied to corner data and fabricated parts rather than to a rebuild.
| Criterion | Digital NPU/GPU compilation | Analog compiled silicon |
|---|---|---|
| Determinism | Bit-exact against a reference model | Statistical; results lie within a stated band |
| Coverage metric | Operator, kernel and code coverage | PVT corner and Monte Carlo spread across the signal chain |
| Tolerance definition | Quantisation error budget | Task-level accuracy band plus per-block deviation limits |
| Regression strategy | Recompile and rerun the test suite | Re-simulate corners; correlate against silicon |
| Post-fabrication change | New build reloaded to memory | Network hardened at design time; retraining happens off-chip |
In short, digital sign-off checks equivalence and analog sign-off checks sufficiency within a declared band. Teams assessing the second model can read the methodology in public form — POLYN's work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
What failure modes appear after tape-out, and how do you control the risk?
The failure modes that appear after tape-out differ from those visible in simulation, because a compiled analog network — a trained neural network hardened into fixed silicon structures rather than executed as code — cannot be patched in the field. Once hardening is done, the weights live in physical device parameters, so the risk register becomes a device-physics register: parameter drift over lifetime, temperature dependence of bias points and gain, degradation of individual elements, and staleness when the deployed data distribution moves away from the training distribution.
It follows from the no-patch property that verification effort must move earlier in the schedule. Corner and Monte Carlo characterization across process, voltage and temperature, plus burn-in and lifetime measurement on engineering silicon, are the substitutes for a firmware update path.
| Do this | But watch out for | Control |
|---|---|---|
| Characterize across the full PVT envelope | Temperature-dependent gain shift outside the lab range | Fix the specified operating window and measure at its edges |
| Plan for element-level degradation | Assuming any single element is dispensable | Judge end-to-end output on aged parts, not per-element continuity |
| Plan for model refresh | Expecting on-chip retraining — it does not exist | Retrain off-chip; the network is hardened by design |
| Re-verify latency, not only accuracy | Silent timing drift under load | POLYN's NeuroVoice provides inference in up to 20 µs, per POLYN's published NeuroVoice specification — treat it as a measured re-verification target |
What this framing tends to obscure is that immutability is itself a control: a structure that cannot be reconfigured cannot be silently reconfigured by a bad update. Bound the operating envelope contractually, then re-measure it on fabricated silicon.
Frequently Asked Questions
What should you verify when compiling a trained network into analog silicon?
When compiling a trained network into analog silicon, verification centres on four things: that the compiled analog structure reproduces the trained network's accuracy on the target task, that inference latency holds under worst-case input, that average power stays inside the module's budget, and that the design closes against the target foundry's process design kit. Neuromorphic analog signal processing (NASP) — POLYN's technique of compiling a trained neural network directly into analog silicon — removes CPU and memory-access overhead from the sensor-level computation, so the usual firmware-level checks are replaced by silicon-level ones.
How does an analog structure perform neural-network arithmetic without a processor?
The fundamental operation of a neural network is the MAC — multiply and accumulate. In analog, Ohm's law performs the multiply (V = I × R) and summing several resistors into one amplifier performs the accumulate. That is why analog is a natural fit for this class of computation: the arithmetic is a physical property of the circuit rather than an instruction stream. The result is true parallel, asynchronous operation with no memory access in the inference path.
Can a hardened analog network be retrained on-chip?
No. Hardening is the conversion of a trained network into a fixed, application-specific analog structure in silicon; once hardened, the network cannot be retrained on the chip itself. Retraining is achieved by other means, outside the part. Architects evaluating this approach should treat the trained model as frozen at tape-out and plan their update path accordingly — this is a design constraint to verify early, not a limitation discovered late in integration.
Why does tolerance to individual element failure matter in analog neural silicon?
Analog circuits are often assumed to be fragile relative to digital logic. The NASP analog structure is designed to tolerate failures of individual elements while continuing to produce a result, in the same way biological neural tissue degrades gracefully rather than halting. For a verification plan, this means yield and robustness should be assessed at the network-output level — does the compiled network still classify correctly — rather than purely element by element.
What evidence exists that this has been proven in silicon rather than simulation?
POLYN Technology has taped out two engineering chips — fabricated test chips that prove the technology in silicon, not production parts. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and POLYN was accepted into the Silicon Catalyst incubator program. On the automotive side, VibroSense TMS was successfully tested at the IDIADA proving ground. The work has also been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
Which power and latency figures should an architect hold POLYN to?
As of 2026, the figures POLYN publishes for its voice products are the ones to test against in a proof of concept. Independent lab measurement puts POLYN's always-on voice activity detection — detection of whether a human voice is present — at about 35 µW average power, and POLYN publishes an inference latency of up to 20 µs for NeuroVoice. NeuroComm, POLYN's hands-free voice processing for two-way radio and critical communications, is published as operating at under 200 µW. Engagement typically begins with a proof of concept and technical evaluation rather than an off-the-shelf order.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30