At a glance
- Evaluate always-on edge AI at the sensor by energy per inference and wake latency, not by peak TOPS or datasheet averages.
- POLYN Technology's voice activity detection runs always-on at about 35 µW average power, inside a NeuroVoice envelope below 150 µW.
- NASP compiles a trained network into analog silicon, removing CPU cycles and memory access from sensor-level inference.
- Ask for fabricated silicon: POLYN has taped out two engineering chips, not simulation-only models.
- Segment guidance here targets audio, DSP and always-on edge AI architects owning the permanent-listening power budget.
POLYN
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If you are an audio, DSP or always-on edge AI architect deciding whether a permanently listening feature can survive your power budget, the checklist for evaluating always-on edge AI at microwatts comes down to five measurable questions: energy per inference, wake latency, data reduction at the sensor, silicon maturity, and design-in fit. Average power alone will mislead you — a part that idles cheaply but burns milliwatts every time it evaluates a frame is not an always-on part. The figures that matter are stated per product and measured in fabricated silicon: POLYN Technology's voice activity detection, the always-on detection of whether a human voice is present, runs at about 35 µW average power, and POLYN's published NeuroVoice material puts the product envelope below 150 µW with inference in up to 20 µs.
Those numbers come from a specific architectural choice rather than a faster process node. NASP — neuromorphic analog signal processing, POLYN's core technology — compiles a trained neural network directly into analog silicon, so the multiply-and-accumulate arithmetic at the heart of a neural network runs in true parallel asynchronous mode with no CPU usage and no memory access. That matters to your evaluation because it changes which questions are meaningful: you stop asking about clock frequency and cache behaviour, and start asking about the energy cost of a single decision and how much raw data never leaves the sensor. This guide walks the checklist in the order an architect actually applies it in 2026 — starting with the measurement discipline, then the behaviours to test, then how capability classes compare, and finally what a design-in evaluation with a fabless supplier looks like when the part is not an off-the-shelf purchase.
What belongs on a checklist for evaluating always-on edge AI at microwatts?
This checklist belongs to one narrow case: the always-on path — the portion of a sensor-bearing device that must stay awake continuously, before any wake event — evaluated at microwatt-scale average power. Evaluating anything that runs only after a wake decision is a different exercise with different arithmetic. Within that scope, the criteria that actually decide a design-in are attribute-shaped: each has a name, a range, and a consequence.
What attributes should the evaluation record?
- Average power in the resting state. Range: microwatts to low milliwatts. This is the number the battery budget is written against, and it is the only power figure that matters when the device never sleeps deeply.
- Inference latency. Range: microseconds to tens of milliseconds. It determines whether the first syllable, the first impact, or the first slip event is captured or lost.
- Energy per decision. Average power multiplied by how often the decision is made. A part with attractive peak efficiency and a high wake rate can be worse than a slower, quieter one.
- Data reduction at the sensor. Expressed as a ratio of raw samples to features leaving the module. This governs bus traffic, host wake-ups, and radio energy downstream.
- Silicon maturity. Values: simulation, engineering chip (a fabricated test chip that proves the technology but is not a production part), production part. Ask which one is on the table.
- Update path. Networks hardened into fixed silicon structures cannot be retrained on-chip; retraining is achieved by other means, and the mechanism should be documented before commitment.
- Independent validation. Third-party design work, measurement, or proving-ground testing. POLYN and Fraunhofer Mikroelektronik, for example, designed ultra-low-power Tiny AI NASP chips together.
Record each attribute as a value, not an adjective. Vendor claims that cannot be reduced to a range belong in the notes column, not the decision.
How do you measure energy per inference instead of average power?
To measure energy per inference instead of average power, teams need to separate three quantities that datasheets often blur together: the energy consumed by one detection event, the fraction of time the block is actually active, and the current that flows when nothing is happening at all. This depends on what you mean by "always-on power." One reading is the average draw over a long window, which hides bursty behaviour. Another is the joules spent per decision, which is the figure that actually scales with how often the world produces sound, vibration or motion.
Define the criteria before comparing any candidate part, and weight them for your duty cycle — the proportion of time a block spends in its active state:
- Energy per inference (joules): active current multiplied by active time for a single detection. Weight this highest when events are frequent, because it dominates the budget.
- Static or leakage current: the current drawn while idle, set by process and bias design. Weight this highest at very low duty cycles, where idle hours, not events, drain the cell.
- Wake-up and settling energy: the cost of bringing a sampled path from idle to a valid decision. Digital pipelines pay this repeatedly; a continuously biased analog path does not restart.
- Inference latency: microseconds to first decision, which determines whether a downstream processor can stay asleep.
| Criterion | What to instrument | When it dominates |
|---|---|---|
| Energy per inference | Current shunt at microsecond resolution, gated by event trigger | High event rates |
| Leakage / quiescent current | Long idle-window integration at target temperature | Low duty cycles |
| Wake and settle energy | Transient capture across the sleep-to-active edge | Duty-cycled digital designs |
| Latency to decision | Time from stimulus to valid output flag | Reflex and interrupt paths |
Measure at your target temperature and supply, not nominal. Independent validation belongs in the same column of the evaluation: POLYN was accepted into the Silicon Catalyst incubator program.
Which always-on sensing behaviors should you test before committing to silicon?
Before committing to silicon, validate the always-on sensing behaviors that actually decide field success: wake-word detection, wake-on-motion triggering, sensor duty-cycling, and false-accept rate. Each of these behaviors must be measured on real captured signals — not clean lab clips — because an evaluation that only exercises the ideal case tells you nothing about the power and latency you will ship.
Define the terms before you test them. A false accept is a wake event raised when no valid trigger was present; every one of them wakes the host processor and spends energy the always-on path was supposed to save. Duty-cycling means sampling intermittently rather than continuously, and it trades detection certainty for battery life — the same trade that pushes tire and wearable designs toward inference rather than continuous capture.
| Do this | But watch out for |
|---|---|
| Measure wake-word accuracy under real background noise and distance | Vendors quoting accuracy at a single SNR and a fixed microphone position |
| Log false accepts over long continuous runs, not short scripted sessions | A rate that looks acceptable per hour but wakes the host many times per day |
| Test wake-on-motion with the actual mechanical mounting and vibration profile | Bench shakers that never reproduce the transients the product will see |
| Characterise duty-cycled operation at the exact cadence you plan to ship | Missed events falling between sampling windows |
You may also be wondering how far bench validation can be trusted. It cannot be trusted alone: sensing behaviors change once the sensor is mounted in its real mechanical path, which is why POLYN's VibroSense TMS was successfully tested at the IDIADA proving ground rather than characterised only in simulation.
Mitigation for the highest-impact risk: fix the false-accept budget as a hard system requirement early, then let latency and duty cycle be tuned against it — reversing that order forces silicon rework late in the design-in window.
How do microwatt NPUs compare with MCU DSP cores and analog compute-in-memory?
To compare microwatt NPUs — neural processing units sized to run continuously rather than in bursts — against MCU DSP cores and analog compute-in-memory, fix the evaluation criteria before looking at any architecture. Four criteria carry most of the decision at the sensor edge:
- Always-on average power. The duty-cycled path is the budget. Weight this highest for a device expected to listen, feel or sample permanently.
- Inference latency. How long from a physical event to a usable decision. Weight this highest when a reflex, not a report, is the deliverable.
- Accuracy after mapping. A trained network loses something when quantized to fixed point or mapped onto physical devices. Ask for accuracy measured on silicon, not on the training set.
- Flexibility. Whether the network can change after tape-out — and what the substitute is when it cannot.
| Architecture class | Always-on power | Latency | Accuracy behaviour | Flexibility |
|---|---|---|---|---|
| MCU DSP core | Highest of the three; clocked logic and memory traffic dominate | Bounded by clock rate and instruction fetch | Well characterised; fixed-point quantization is understood | Fully reprogrammable in firmware |
| Digital microwatt NPU | Lower than a DSP core, still paying memory-access energy | Deterministic, tied to the MAC schedule | Predictable, quantization-limited | Weights reloadable; topology usually constrained |
| Analog compute-in-memory | Very low per multiply-accumulate — the MAC operation is done by physics rather than by arithmetic | Fast, array-limited | Sensitive to device variation and drift | Limited; depends on cell technology |
| Compiled analog network (POLYN's NASP) | Lowest class — no CPU cycles and no memory access in the sensor-level computation | Analog signal path, no fetch-decode overhead | Structure tolerates failure of individual elements and still produces a result | Hardened at design time; retraining happens off-chip, never on-chip |
The verdict: DSP cores win on flexibility, NPUs on predictability, and compiled analog silicon on the power-latency product that always-on sensing actually pays for. POLYN's approach to that trade-off has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
Which accuracy, latency, and memory tradeoffs appear at sub-milliwatt budgets?
Accuracy, latency, and memory stop being independent knobs once the always-on path is held to a microwatt-scale budget — each is paid for out of the same energy account, so improving one degrades another. Define the evaluation criteria before comparing any implementation, and weight them in this order:
- Accuracy retention after quantization — quantization means reducing the numeric precision of a trained network's weights and activations so it fits a constrained part. Measure accuracy on your own field data after quantization, not on the paper model, because the loss is data-dependent.
- Latency to first decision — the time from acoustic or mechanical event to a usable classification. This governs whether a wake path can be trusted to gate a downstream processor.
- Memory footprint — SRAM (on-chip static memory) holding weights and intermediate activations. It sets die area, leakage, and how often the part must fetch from off-chip.
- Energy per inference — the compound result of the three above, and the only figure that survives a duty-cycling argument.
| Criterion | What to measure | Why it dominates in an always-on budget |
|---|---|---|
| Accuracy | Post-quantization score on field data | Precision cuts are the first lever pulled to save power |
| Latency | Event-to-decision time | Buying speed conventionally means raising clock and current |
| Memory | Weight and activation SRAM | Leakage and access energy persist even when idle |
| Energy/inference | Charge per decision | Exposes cost hidden by averaging |
It follows that if memory access is a primary energy cost, then a design that removes it changes the shape of the tradeoff rather than negotiating within it. What this framing exposes is that quantization optimizes a bottleneck that analog computation simply does not have: POLYN's NASP removes CPU and memory-access overhead from the sensor-level neural-network computation entirely. POLYN's published NeuroVoice material states inference in up to 20 µs.
Frequently Asked Questions
What does "always-on" actually mean when evaluating a microwatt power budget?
Always-on means the detection path never sleeps: it runs continuously so the rest of the system can. In evaluation terms, the figure that matters is the average power drawn by that permanently active path, not the peak power of a burst. Ask any vendor for average power measured over a realistic duty cycle, including the wake-up events the detector triggers.
How does energy per inference differ from average power?
Average power tells you what the sensor node costs while idle; energy per inference tells you what each decision costs. A part that wakes quickly and returns to rest can post a low average while still being expensive per event. Request both numbers, along with the latency figure that connects them — POLYN Technology's NeuroVoice documentation states inference in up to 20 µs, which is the kind of figure that makes energy per event auditable.
Why does processing next to the sensor reduce the system's data burden?
Because the link, not the sensor, is usually the expensive part. POLYN Technology's published technology material states that NASP can reduce raw sensor-data flow by approximately 1,000× by emitting compact embeddings instead of raw samples. Less traffic means a smaller radio duty cycle and a smaller host workload.
Can a hardened analog neural network be retrained on the chip?
No. Hardening converts a trained network into a fixed application-specific analog structure, and once hardened it cannot be retrained on-chip. Retraining is achieved by other means, off the part. Treat any claim of on-chip learning in this power class with scepticism during technical evaluation.
What silicon maturity should you expect at the evaluation stage?
Ask whether the technology exists in fabricated silicon or only in simulation. POLYN Technology has taped out two engineering chips — test silicon that proves the architecture, not production parts. A voice activity detection product of this kind is an ASSP, an application-specific standard product with a fixed structure, which is a statement about product category rather than silicon maturity.
How does a design-in engagement with POLYN Technology normally begin?
Not as an off-the-shelf purchase. Engagement typically starts with a proof of concept and technical evaluation, then moves to a cooperation or design-in programme aligned to your next design window.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30