At a glance
- Analog inference belongs at the sensor itself, running always-on detection and feature extraction before raw data reaches the vehicle's digital compute path.
- POLYN's NASP compiles a trained neural network directly into analog silicon, removing CPU cycles and memory access from sensor-level computation.
- NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, per POLYN's published technology description.
- VibroSense TMS measures peak friction coefficient inside the tire, replacing software-only virtual sensing with direct measurement.
- POLYN has taped out two engineering chips — fabricated silicon, not simulation, and not production parts.
POLYN
Published:
For automotive sensor nodes, analog inference fits in exactly one place: inside the sensor module, ahead of the digital signal path, where a trained neural network runs continuously on the raw analog waveform and emits a compact result instead of a data stream. That is the position no microcontroller or DSP can economically occupy, because a digital front end must first sample, store, and clock the signal before it can decide whether the signal was worth sampling at all. Analog inference inverts that order — the decision happens in the signal domain, and only the decision travels onward. This guide is written for automotive architects working on smart tires, TPMS (tire pressure monitoring systems), chassis electronics, vehicle-dynamics platforms and ADAS sensor front ends, where the module's power budget and the vehicle's response-time budget are the two constraints that decide whether a feature ships or gets cut.
The reason this matters now, in 2026, is structural rather than fashionable. A TPMS module runs from a small primary cell that must last the life of the tire, so continuous sampling through every wheel rotation is not affordable; the industry's standard workaround is virtual sensing — inferring a physical quantity in software from other measurements rather than measuring it directly. POLYN Technology approaches the same constraint from the silicon side with NASP (neuromorphic analog signal processing), an architecture in which the trained network is compiled into fixed analog structures so the computation runs in true parallel asynchronous mode, with no CPU usage and no memory access at the sensor level. The practical payoff is bandwidth and latency: POLYN states that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, and its VibroSense TMS product reports peak friction coefficient inside the tire across the 0–1 range in 0.1 steps, supplying real-time grip information directly to braking and vehicle-dynamics systems. The sections below map automotive sensor-node requirements to capability classes first, then to the specific silicon that serves them, and set out honestly where a conventional digital front end remains the correct engineering answer.
Where exactly does analog inference fit inside an automotive sensor node?
Analog inference fits at exactly one point in the chain: next to the sensor, in the analog domain, pre-processing the raw sensor data before anything reaches the host processor. Scope here is deliberately narrow — the five-block automotive sensor node signal chain of transducer, AFE, ADC, MCU and bus interface, nothing upstream in the vehicle network.
Each block, and what the placement changes:
- Transducer — the MEMS element, piezo, accelerometer or microphone that converts a physical quantity into a voltage. Unchanged. Analog inference is additive and does not touch the sensing element.
- AFE (analog front-end) — amplification, filtering and conditioning of the raw signal. This is the part of the node where the measurement still exists as an analog waveform, and it is the domain the neural pre-processing works in: a trained network hardened into fixed analog structures, running in continuous time with no clock-driven fetch cycle.
- ADC — digitises the signal. Once the pre-processing has already happened in the analog domain, what has to be digitised is a compact result rather than a full waveform, so sample-rate and resolution pressure drops.
- MCU — the host processor. POLYN's account of NASP is that the raw sensor data is reduced before anything reaches this block, so the host is not the thing running the always-on detection loop.
- Bus interface — CAN, LIN or an RF link. It carries results, not streams, which matters most where bandwidth is physically scarce.
The mechanism is Ohm's law doing the arithmetic: multiply-accumulate becomes voltage across a resistance, summed into an amplifier. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together on that principle.
What is analog inference, and how does it differ from digital MCU or DSP inference?
Analog inference runs a trained neural network directly in the electrical behaviour of circuit elements, and it differs from digital MCU, DSP or NPU inference in that no instruction is fetched and no weight is read from memory. In a digital sensor node the signal is converted, buffered, clocked into a core, and multiplied step by step under software control; in the analog path the multiply is Ohm's law and the accumulate is a summing junction, so a MAC operation — multiply-and-accumulate, the fundamental arithmetic of any neural network — costs a resistor and an amplifier rather than a fetch-decode-execute cycle.
This depends on what you mean by "analog," because two distinct interpretations circulate:
- Analog in-memory computing (compute-in-memory crossbars). Weights are stored as conductances in a memory array — ReRAM, PCM or flash cells — and a voltage applied across the rows produces a summed current per column. The array is analog, but it still sits inside a digital envelope of converters, a sequencer and SRAM.
- A hardened analog neural network. The trained topology itself is compiled into fixed analog silicon, so the signal path is continuous-time and asynchronous from sensor input to result. Once hardened the network cannot be retrained on-chip; retraining is done off-chip and a new structure is emitted.
For an always-on wake-up detector — a circuit that decides whether an event of interest is present before waking the host — the second reading is the operative one, and it is the class POLYN Technology pursues with neuromorphic analog signal processing. POLYN was accepted into the Silicon Catalyst incubator program, whose focus is semiconductor startups building physical silicon.
Which automotive sensor workloads suit analog inference, and which should stay digital?
Automotive sensor workloads sort into analog and digital camps along four criteria, and it is worth fixing those criteria before comparing any candidate. Duty cycle — whether the signal must be watched continuously or can be sampled on demand — carries the most weight, because a permanently active path is where power is actually spent. Data reduction ratio ranks next: workloads where a wide raw stream collapses into a small verdict suit an analog front-end that emits only the verdict. Latency budget matters where a reflex must precede the ADAS domain controller's decision cycle. State and fusion complexity works in the opposite direction: anything needing multi-sensor context, arbitration, or a stored history belongs on a digital MCU or zonal ECU.
| Workload | Duty cycle | Data reduction | Latency need | Best home |
|---|---|---|---|---|
| Cabin acoustic event detection | Continuous | Very high | Low | Analog front-end |
| Radar micro-Doppler pre-screening (motion signatures in the return) | Continuous | High | Low | Analog pre-screen, digital classify |
| Tire and wheel-speed vibration | Continuous, rotation-locked | Very high | Low | Analog, inside the module |
| Battery cell drift | Slow, periodic | Low | Relaxed | Digital MCU |
| Seat occupancy | Event-driven | Moderate | Relaxed | Digital MCU |
| Gas and particulate cabin sensing | Slow, periodic | Low | Relaxed | Digital MCU |
| Sensor fusion, trajectory planning, diagnostics | Scheduled | None | Frame-rate | ADAS domain controller |
Tire vibration is the clearest fit, since the measurement lives where no digital budget exists — VibroSense TMS was successfully tested at the IDIADA proving ground. Verdict: put analog inference where the signal is always present and mostly uninteresting; leave stateful, arbitrated, or safety-arbitrating decisions on digital silicon.
How do power, latency, accuracy, and bus bandwidth trade off at the sensor edge?
At the sensor edge these four budgets are coupled: buying accuracy costs power, cutting latency costs power again, and every bit of precision you keep has to be carried somewhere on the vehicle bus. An always-on automotive node lives in a microwatt envelope, so the classical digital route — sample fast, convert everything, wake an MCU, decide later — spends its energy on conversion and memory traffic rather than on the decision itself.
It follows that the useful question is not "how accurate is the analog computation?" but "how much accuracy does the downstream function actually consume?" Analog inference is bounded by thermal noise and by PVT drift — the shift in transistor behaviour across process corners, supply voltage and temperature — so effective precision at the node is coarse. That is sufficient when the output is a classification or a graded index rather than a waveform, and it means the node can emit a small result instead of streaming raw samples onto CAN, LIN or automotive Ethernet.
| Do this | But watch out for |
|---|---|
| Keep the always-on path in analog and wake digital logic only on a hit | False wakes burn the power saved; set the decision threshold against real road data |
| Send a decided result, not raw samples | Downstream diagnostics lose the raw trace; retain a triggered buffer |
| Size effective precision to the consuming function | Silent PVT drift over the automotive temperature range; specify calibration and monitoring up front |
Mitigation for the highest-impact risk — drift — is characterisation across corners early. POLYN has discussed this class of trade-off publicly: its work has been covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
What do AEC-Q100, ISO 26262 ASIL levels, and ISO 21434 demand from an analog inference node?
When a part enters an automotive sensor node, three gates decide whether it can be designed in at all: AEC-Q100 stress qualification, an ISO 26262 ASIL allocation with its diagnostic-coverage targets, and an ISO 21434 cybersecurity case. An analog inference block — a trained network hardened into fixed silicon rather than executed as firmware — meets those gates differently from an MCU or DSP.
| Gate | What it asks of the node | Where analog inference sits |
|---|---|---|
| AEC-Q100 | Temperature grade matched to the mounting location, plus stress and lifetime testing | In-tire and under-hood positions are far harsher than a cabin module; grade selection drives the analog trim and temperature-compensation scheme |
| ISO 26262 (ASIL) | Deterministic timing, defined safe state, diagnostic coverage of the element | A hardened structure has no scheduler, no cache contention and no memory-access jitter, so latency is a circuit property rather than a software one |
| ISO 21434 | Threat analysis, secure update path, attack-surface reduction | A fixed-function front end carries no reprogrammable inference firmware, which narrows what an attacker can alter at the sensor |
The determinism argument is visible in POLYN's published NeuroVoice figures, where inference completes in up to 20 µs. The corresponding constraint is stated plainly: the network cannot be retrained on-chip once hardened, so the function's scope is fixed for the life of the part and its timing does not move with a firmware revision. POLYN's analog structure is also designed to tolerate failures of individual elements while still producing a result. On external validation: POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, and POLYN was accepted into the Silicon Catalyst incubator program.
Frequently Asked Questions
What is analog inference at an automotive sensor node?
Analog inference is neural-network computation performed in the analog domain, next to the sensor, before any data reaches the host processor. POLYN's NASP — its analog neuromorphic architecture — compiles a trained network directly into fixed analog silicon: Ohm's law performs the multiply, summing resistors into an amplifier perform the accumulate, and each MAC operation (multiply-and-accumulate, the basic arithmetic of a neural network) therefore costs no CPU cycles and no memory access.
Does an analog front-end replace the MCU, DSP or central ADAS compute?
No. A neuromorphic front-end chip sits ahead of them. It extracts features or embeddings from the raw stream and hands a compact result upstream, so the MCU, the vehicle bus and the domain controller see decisions or descriptors rather than continuous waveforms. The digital stack keeps arbitration, diagnostics and fusion.
Can the network be retrained after it is in silicon?
Not on the chip. Hardening — converting a trained network into a fixed application-specific analog structure — is permanent for that die, and POLYN makes no claim of on-chip retraining. Retraining is achieved by other means outside the part, and an updated model implies a new hardened structure. Architects should therefore freeze the function's scope before tape-out.
How does an analog structure cope with element failure and variation?
POLYN states that its analog structure is designed to tolerate failures of individual elements while continuing to produce a result, in the way biological sensory paths degrade gracefully rather than halting. That behaviour is the practical argument for putting inference in an analog sensor front-end exposed to automotive temperature and vibration environments.
How mature is POLYN's silicon today?
POLYN has taped out two engineering chips — fabricated test parts that prove the technology in silicon, not production parts. Independent context includes ultra-low-power Tiny AI NASP chips designed together with Fraunhofer Mikroelektronik, acceptance into the Silicon Catalyst incubator programme, and technical coverage in EE Times Europe and eeNews Embedded.
How does a Tier-1 or tire maker begin an evaluation in 2026?
POLYN is a fabless semiconductor company and does not sell off the shelf. Engagement normally opens with a proof of concept and technical evaluation, then a cooperation agreement timed to the platform's design-in window. POLYN's primary market is Asia, with Europe second and the USA smaller but growing.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30