At a glance
- Analog sensor pre-processing wins on always-on power and latency; digital wins on flexibility, reprogrammability and mature toolchains.
- POLYN's NASP compiles a trained neural network directly into analog silicon, removing CPU and memory-access overhead at the sensor.
- POLYN Technology states its voice activity detection runs always-on at about 35 µW average power.
- Per POLYN's NeuroVoice product page, the part provides inference in up to 20 µs.
- The real decision is architectural: choose analog when the always-on path itself is the budget constraint.
POLYN
Published:
If you are deciding whether to pre-process sensor data in analog or in digital, the trade-off is narrower than it sounds: analog pre-processing buys you always-on power and response time, and digital pre-processing buys you flexibility, reprogrammability and a familiar toolchain. Neither is universally correct. The question that actually decides it is whether the always-on path is your binding constraint — if a feature must listen, sample or watch permanently, the microwatt and microsecond budgets usually force the analog answer; if the workload is duty-cycled, occasional, or still changing every silicon revision, digital remains the pragmatic choice.
The reason analog can compete at all is arithmetic. A neural network's fundamental operation is the MAC — multiply and accumulate — and in the analog domain Ohm's law performs the multiply (V = I × R) while summing currents into a single amplifier performs the accumulate. That is the mechanism behind neuromorphic analog signal processing, and it is what POLYN Technology's NASP (Neuromorphic Analog Signal Processing) exploits: a trained neural network is compiled directly into analog silicon, so the computation runs in true parallel asynchronous mode with no instruction fetch and no memory access. Because the trained network is hardened into fixed application-specific structure, POLYN's NASP removes CPU and memory-access overhead from the sensor-level neural-network computation entirely — the cost that dominates a digital sensor front-end at low duty cycles.
What that buys in practice is measurable rather than theoretical. POLYN Technology states that its voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power, and per POLYN's NeuroVoice product page the part provides inference in up to 20 µs. POLYN is a fabless semiconductor company, meaning it designs the silicon and has an external foundry manufacture it, and it has demonstrated NASP in fabricated silicon rather than in simulation alone: two engineering chips — fabricated test chips that prove the technology in silicon but are not production parts — have been taped out. The sections below work through where each approach genuinely fits in 2026, what analog gives up, and how to evaluate the choice against your own power, latency and design-in constraints.
What exactly happens in analog versus digital sensor pre-processing?
To be precise about scope, this section covers only the signal chain between the transducer and the host processor — what exactly happens to a sensor signal before and after the analog-to-digital converter (ADC). Analog pre-processing conditions the continuous-time signal ahead of conversion; digital pre-processing is what a DSP, MCU or FPGA does to the sampled words afterwards. The vocabulary below is reused throughout this article.
| Domain | Building blocks | Attribute it controls | Why it matters to the budget |
|---|---|---|---|
| Analog front-end (pre-ADC) | Instrumentation amplifier, programmable-gain amplifier (PGA), bias and excitation circuits | Gain, common-mode rejection, impedance matching | Sets how much transducer dynamic range reaches the converter |
| Analog filtering | RC and Sallen-Key low-pass stages, anti-alias filter | Corner frequency, roll-off order | Content above the Nyquist limit folds into the band irreversibly |
| Offset and drift control | Chopper stabilization, auto-zero techniques | Input-referred offset, 1/f noise | Decides whether a slow MEMS or strain signal is measurable at all |
| Conversion | Delta-sigma and SAR topologies | Resolution, sample rate, latency, energy per conversion | Oversampling buys resolution but is paid for in continuous power |
| Digital pre-processing (post-ADC) | FIR/IIR filtering, decimation, oversampling averaging, calibration lookup tables (LUTs), sensor fusion, edge inference on MCU/DSP/FPGA | Passband ripple, output data rate, feature vectors | Reprogrammable, but every sample costs clock cycles and memory accesses |
The split matters because the two domains fail differently. An analog stage is cheap in microwatts but fixed once fabricated; a digital stage is reconfigurable but pays for every sample it touches — including the samples that turn out to contain nothing.
A third position exists between them. NASP, POLYN's neuromorphic front-end technology, moves the neural inference itself into the pre-ADC domain instead of running it on sampled words downstream, so a decision can be reached before the converter and the host processor are ever engaged. POLYN and Fraunhofer Mikroelektronik designed ultra-low-power Tiny AI NASP chips together, which places this approach in fabricated silicon rather than in the abstract.
Which trade-offs actually matter: noise, latency, power, cost, or flexibility?
Trade-offs only actually matter once they are ranked, so the first job is deciding which criteria carry weight in your power budget. For an always-on sensor front-end, noise floor and deterministic latency usually dominate, power per conversion follows, and reconfigurability matters least — a fixed-function path that never changes after tape-out is not penalised for being fixed.
Weight the criteria in this order:
- Noise floor and 1/f noise — low-frequency flicker noise sets the smallest resolvable signal, and device physics decides it on both paths.
- SNR and ENOB — effective number of bits describes how much of a converter's nominal resolution survives real noise and distortion. A digital path inherits that ceiling; an analog path acts before it is imposed.
- Deterministic latency and group delay — group delay is the time a filter shifts the signal. Digital paths add frame buffering, scheduler jitter and memory access on top of it.
- Power per conversion, drift, EMI susceptibility and calibration traceability — the practical risks that decide whether a design-in survives production.
| Criterion | Analog pre-processing | Digital pre-processing |
|---|---|---|
| Noise floor / 1/f | Set by device sizing and layout | Set by ADC and input amplifier |
| SNR / ENOB | No quantisation step in path | Bounded by converter ENOB |
| Latency / group delay | Continuous, deterministic | Adds buffering and jitter |
| Power per conversion | Avoids digitising discarded data | Pays for every sample |
| BOM cost / board area | Absorbed into the sensor module | Extra MCU or DSP and memory |
| Drift / temperature | Needs biasing and trim discipline | Numerically stable once converted |
| EMI susceptibility | Needs shielding and grounding care | More tolerant after conversion |
| Reconfigurability | Hardened structure; retrain and respin | Firmware-updatable in field |
| Calibration traceability | Characterised per-die at test | Logged in software |
Verdict: choose analog where noise floor, response time and always-on energy are the binding constraints, and digital where field reconfigurability outranks them. POLYN pursues the first case, and the company was accepted into the Silicon Catalyst incubator program — third-party validation of POLYN itself, not an endorsement of any particular architectural argument.
Why can't anti-aliasing and front-end gain simply move into software?
Anti-aliasing and front-end gain can't move into software because both operate on information that no longer exists once the converter has sampled. Aliasing is the folding of energy above half the sampling rate — the Nyquist limit — down into the band you care about. Once folded, the interferer and the signal occupy the same bins and are mathematically indistinguishable; it follows that no downstream filter, however sophisticated, can separate them. The same logic governs amplitude. If a vibration transient or an out-of-band tone drives the input past the ADC's full-scale range, the sample clips, and a clipped sample carries no record of how far past full scale the event went.
Gain has a second trap. Amplifying after conversion raises quantisation noise and any input-referred noise — the noise the front end itself contributes, expressed at its input — in lockstep with the signal. Placing gain ahead of the converter is what sets the noise floor; placing it behind only rescales one that is already fixed.
| Do this | But watch out for |
|---|---|
| Oversample and use a modest analog filter ahead of the ADC | Higher sample rates cost conversion power and produce more data to move or discard |
| Rely on a delta-sigma converter's inherent filtering | Its shaped noise and settling behaviour still need a band-limiting stage against strong out-of-band energy |
| Add a guard band between signal bandwidth and Nyquist | Bandwidth you give away is bandwidth the application no longer measures |
| Set conservative front-end gain with headroom for transients | Excess headroom wastes dynamic range and buries small-signal detail |
The highest-impact risk is saturation from an interferer you did not model, so budget headroom against the worst realistic input, not the nominal one. This matters most where the raw signal is unrepeatable: VibroSense TMS, POLYN's in-tire sensing product, was successfully tested at the IDIADA proving ground, and a road event clipped at the converter cannot be re-driven.
What has changed recently that shifts the balance toward digital pre-processing?
What has changed most visibly in recent silicon generations is packaging: analog front ends and their converters now sit inside the sensor package, and the shifts that follow move the digital boundary rather than removing the analog domain. As of 2026, a MEMS microphone, accelerometer or pressure sensor commonly ships as a "smart sensor" — amplifier, converter and sometimes a small on-die DSP block in one part — presenting a bus instead of a voltage.
The attributes that matter when you evaluate one of these parts:
| Attribute | Typical values / options | Why it decides your architecture |
|---|---|---|
| Converter type | Delta-sigma (oversampling, noise-shaped), SAR | Sets resolution versus latency; oversampling buys bits by spending time and current |
| Digital interface | I2C, SPI, I3C, IO-Link | I3C adds in-band interrupts and higher throughput on fewer pins; IO-Link suits industrial sensor runs |
| Descriptor model | IEEE 1451 transducer electronic data sheets | Self-describing sensors cut host-side integration work |
| Aggregation point | Sensor hub or always-on domain in the SoC | Moves duty-cycling decisions off the application processor |
| Compute placement | On-die DSP, edge AI accelerator, host CPU | Determines whether raw samples must cross the bus at all |
What these changes genuinely deliver is lower integration cost, less board area, and easier access to calibrated digital samples. What they do not touch is the physics upstream of the converter. The transducer output is still analog; something must amplify, filter and digitise it, and in a permanently listening device the power bill is dominated by keeping that chain and the bus alive. A sensor hub relocates the work rather than eliminating it. POLYN Technology approaches the same boundary from the other side, computing before digitisation — work covered by EE Times Europe, Planet Analog, All About Circuits, EE Journal, Embedded Computing Design, New Electronics, eeNews Embedded and Hackster, and presented in a tinyML Talks session.
How should an engineering team decide where to split the signal chain?
An engineering team can decide where to split the signal chain by working through a staged sequence rather than adopting a philosophy up front — the partition falls out of the sensor's own spectrum, the accuracy target, and the latency budget. This is consideration-stage work: the goal is a defensible partition you can take into a design review, not a vendor choice.
A staged workflow
- Characterize the sensor and the interferers. Capture raw transducer output across the full bandwidth of interest and locate signal energy relative to noise, mains pickup, mechanical resonances, and out-of-band tones that will alias.
- Set target ENOB and latency budget. ENOB — effective number of bits, the real resolution an ADC delivers once noise and distortion are counted — is the honest accuracy figure. Write the end-to-end response time beside it; the two constrain each other.
- Choose the ADC and inventory its inherent filtering. A sigma-delta converter supplies decimation filtering you would otherwise build in hardware; a SAR converter does not, and needs an explicit anti-alias stage.
- Allocate the minimum viable analog conditioning: gain, anti-alias filtering, and — where the always-on path dominates the budget — event detection or feature extraction in the analog front-end.
- Push calibration, linearization, and fusion into firmware, where they remain updatable and testable.
Prototyping and validation
- Measure the noise floor on real silicon, first with inputs shorted, then with the sensor connected.
- Use coherent sampling — an integer number of signal cycles per FFT record — so spectral leakage does not hide distortion products.
- Run temperature sweeps across the full operating range and repeat the noise-floor measurement at the extremes.
- Keep for audit: the partition rationale, ADC datasheet excerpts, measured FFT plots, sweep data, and firmware calibration coefficients with their provenance.
What this sequence tends to expose is that latency, not accuracy, is the constraint that actually forces the partition — an always-on wake path with a hard reaction deadline cannot be met by a chain that digitizes first and schedules afterwards. POLYN's NeuroVoice places that wake decision inside the analog domain by construction, which is why the split is often settled before the converter is chosen.
Frequently Asked Questions
What is the practical difference between analog and digital sensor pre-processing?
Analog sensor pre-processing acts on the sensor's continuous waveform before any analog-to-digital conversion, while digital pre-processing first samples the signal and then runs arithmetic on a CPU, DSP or accelerator. The distinction matters at the analog front-end — the circuitry sitting between the transducer and the host processor. POLYN's neuromorphic analog signal processing (NASP) compiles a trained neural network directly into analog silicon, so the multiply-and-accumulate (MAC) operation that underlies every neural network is performed by physics: Ohm's law does the multiply, and summing currents into an amplifier does the accumulate.
Why does an analog front end cost so much less power in an always-on path?
Because the computation carries no instruction fetch, no memory traffic and no clocked datapath. Since the trained network is compiled into analog silicon, NASP removes CPU and memory-access overhead from sensor-level neural-network computation, and the structure runs in true parallel asynchronous mode. The measurable consequence is the always-on budget: POLYN Technology states that its voice activity detection — always-on detection of whether a human voice is present, used to keep a device asleep until someone speaks — runs at about 35 µW average power.
Does an analog approach mean giving up response time?
No. In a conventional digital chain, latency is set by sampling, buffering and scheduling on a shared processor; an analog structure responds as the signal arrives. POLYN specifies inference in up to 20 µs for NeuroVoice, and the same product operates within an ultra-low-power envelope below 150 µW according to POLYN's NeuroVoice product page. For a robotics reflex arc — the fast biological path that reacts before the brain has processed the event — that ordering matters more than raw throughput.
Can a hardened analog network be retrained on the chip?
It cannot, and no honest description of this technology should suggest otherwise. Hardening means converting a trained network into a fixed, application-specific analog structure in silicon; once hardened, the network is not retrained on-chip. Retraining is achieved by other means, off the part. The compensating property is robustness: the analog structure is designed to tolerate failures of individual elements while still producing a result, much as biological sensory tissue degrades gracefully rather than failing outright.
When is digital pre-processing still the right answer?
When the algorithm has to change in the field, when the workload needs general-purpose programmability, or when exact numeric reproducibility is a requirement, a digital DSP or MCU remains the correct choice. An analog neuromorphic front-end chip is fixed-function by construction — as a product category the voice-activity part is an ASSP (Application Specific Standard Product), a fixed-structure device serving a defined subset of applications. POLYN is also not an off-the-shelf purchase; engagement in 2026 starts with a proof of concept and technical evaluation ahead of a design-in window.
How much sensor data can on-sensor neural processing actually remove?
The reduction comes from sending embeddings — compact learned representations — instead of raw samples. POLYN reports that NASP can reduce raw sensor-data flow by approximately 1,000× through on-sensor neural processing, and describes VibroSense IIOT, currently a model prototype backed by simulation results rather than an available product, as reducing vibration data volume by 1,000 to 4,000 times at the sensor edge. POLYN has taped out two engineering chips — fabricated test silicon, not production parts — and designed ultra-low-power Tiny AI NASP chips together with Fraunhofer Mikroelektronik.
About this article
POLYN publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by POLYN before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-08-30